Sequential circuit element including a single clocked transistor

A circuit device comprising:

• a first input element comprising a first input and a first output;
• a second input element responsive to the first output and comprising a second output;
• and a retention circuit configured to selectively couple the second output to a first supply terminal, wherein the retention circuit comprises a first transistor responsive to the first output to selectively block a current path between the second output and the first supply terminal;
• and
• further comprising a single clocked transistor configured to provide a virtual voltage level to the first input element and to the second input element when the single clocked transistor is activated, and wherein when the single clocked transistor is deactivated while the second data has a first logical value, the current path is held in a conductive state by the first transistor responsive to the keeper device and by the second transistor responsive to the inverter.

A circuit device comprising:

• a first input element comprising:
• a first input and a first output;
• a second input element responsive to the first output and comprising a second output;
• a retention circuit configured to selectively couple the second output to a supply terminal, wherein the retention circuit comprises a first transistor responsive to the first output to selectively block a current path between the second output and the supply terminal;
• and
• a single clocked transistor configured to provide a virtual voltage level to the first input element and the second input element when the single clocked transistor is activated,
• wherein the first input element is configured to receive input data at the first input and to provide first data at the first output, and wherein the second input element is configured to receive inverted input data and to receive the first data, the second input element further configured to provide second data at the second output.

A circuit device comprising:

• means for receiving input data and generating first data at a first data output;
• means for receiving the first data and generating second data at a second data output;
• and
• retention means for selectively coupling the second output to a first supply terminal, wherein the retention means comprises a first transistor responsive to the first output to selectively block a current path between the second output and the first supply terminal.