Frequency-doubling delay locked loop
AssigneeMosaid Technologies Incorporated
InventorPaul W. Demone
Life of this patent
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Abstract
A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.
Claims10
A delay locked loop for providing an output clock signal in response to a reference input clock signal, the delay locked loop comprising:
- a delay line having a plurality of serially coupled delay stages, each of the delay stages providing a delay stage output;
- a plurality of combining circuit cells, each of the combining cells having inputs respectively coupled to ones of a predetermined number of delay stage outputs, each of the combining cells providing first and second complementary outputs, the outputs of each cell being separated in time by said predetermined number of delay stage outputs;
- a selector responsive to a selection control signal for selecting an output from one of a pair of complementary outputs of one of the combining cells, to produce the output clock signal;
- and
- a phase detector responsive to the output clock signal and the reference input clock signal to generate the selection control signal.
A method for producing an output clock signal in response to a reference input clock signal, the method comprising:
- providing delay stage outputs using a plurality of serially coupled delay stages;
- providing a plurality of pairs of first and second complementary outputs, the outputs of each pair being separated in time by a predetermined number of delay stages;
- comparing the output clock signal and the reference input clock signal to generate a selection control signal;
- and
- selecting, based on the selection control signal, an output from one of the pairs of complementary outputs to produce the output clock signal.
Dependencies are inferred from the claim text.