US 7,746,131 B2 · Reset signal filter

Abstract

A reset signal filter includes a power voltage detector and a reset signal detector or includes only one reset signal detector. The power voltage detector includes a comparators and a basic logic gates (e.g. AND gate, OR gate, inverter, etc). The reset signal detector includes a comparator, N flip flops connected in series, an AND gate, an OR gate, a multiplexer and an output flip flop. The reset signal filter receives a first reset signal generated by a power voltage detector or a Schmitt trigger buffer and utilizes N flip flops to register the signal level of the first reset signal for N clock periods. Then the reset signal filter determines if the first rest signal is changed during N clock periods, and outputs a second reset signal.

Claims16

Dependent claims

A reset signal filter, comprising:

a first comparator for comparing a power voltage and a first reference voltage so as to generate a first comparison signal;
N flip-flops connected in series, a reset port of each flip-flop receiving the first comparison signal, an input port of each flip-flop being coupled to an output port of a preceding flip-flop, an input port of the first of the N flip-flops receiving a first reset signal, the N flip-flops connected in series registering levels of the first reset signal during N clock periods;
a first logic gate, having N input ports coupled to output ports of the N flip-flops connected in series respectively, for determining if the levels of the first reset signal are identical during N clock periods and generating a logic signal;
and
an output flip-flop, being coupled to the first logic gate, for receiving the logic signal and outputting a second reset signal.

2 more elements

Dependencies are inferred from the claim text.

Reset signal filter

Life of this patent

Reset signal filter

Life of this patent

Abstract

Claims16