Ultra low power servo-controlled single clock ramp generator with amplitude independent to clock frequency

A method for generating a ramped voltage having controlled maximum amplitude, comprising:

• generating a pulse comparison clock signal and a reset pulse clock signal having well defined time intervals between pulses in the pulse comparison clock signal and the reset pulse clock signal;
• and
• periodically charging and discharging a ramp capacitor to generate the ramped voltage, comprising:
• monitoring the ramped voltage with a switched comparator by comparing the ramped voltage with a reference voltage during each pulse in the comparison clock signal to develop a ramp correction signal that is captured during each pulse in the reset pulse clock signal, and
• correcting the ramped voltage with each pulse in the reset pulse clock signal by discharging the ramp capacitor during each pulse in the reset pulse clock signal and then charging the ramp capacitor with a ramp current that is generated in response to the ramp correction signal.

A circuit for generating a ramped voltage having a controlled maximum amplitude over a plurality of cycles in an input clock signal, comprising:

• a pulse generator for generating a pulse comparison clock signal and a reset pulse clock signal from a single input clock signal so that pulses in the pulse comparison clock signal are substantially centered between pulses in the reset pulse clock signal;
• a switched comparator having a first input coupled to receive a reference signal, a second input coupled to receive the ramped voltage in feedback, a comparator output node, and an enable node coupled to receive a pulse comparison clock signal, wherein the switched comparator is configured to produce a comparison signal which indicates a difference between the ramped voltage and the reference signal in response to being enabled by the pulse comparison clock signal;
• a correction circuit for generating a target control voltage at an internal charging capacitor in response to the comparison signal;
• a voltage-to-current converter circuit for generating a ramp current in response to the target control voltage;
• a ramp capacitor which is periodically charged and discharged in a controlled fashion by receiving the ramp current so as to develop the ramped voltage having a controlled maximum amplitude at the output node over a plurality of cycles of the single input clock signal, where the ramp capacitor is discharged at each pulse of the reset pulse clock signal.