Input buffer for semiconductor memory apparatus

An input buffer, the input buffer comprising:

• a buffer unit configured to operate when an activation control signal is activated, compare the voltage of an input signal to a preset reference voltage, and output a result of the comparison as an output to an output node, wherein the buffer unit includes:
• first and second PMOS transistor configured to receive the activation control signal, and first and second NMOS transistor configured to receive the input signal and the preset reference voltage, respectively;
• and a third NMOS transistor configured to supply a ground voltage to the first and second NMOS transistors when the activation control signal is activated, and activate the buffer unit;
• and wherein the buffer unit further includes third and fourth PMOS transistor coupled in parallel to the first and second PMOS transistors, respectively, and configured to selectively supply a power supply voltage to the first and second NMOS transistors according to the activation control signal
• an output driver coupled to the buffer unit and configured to control the driving of the output of the buffer unit, and output an output signal;
• and
• a pull-down control unit coupled to the buffer unit and configured to receive the input signal and the output signal of the output driver, output a pull-down control signal having a high pulse for a predetermined time when a change in potential of the input signal occurs, and perform pull-down driving on the buffer unit in response to an enabling of the pull-down control signal.

An input buffer, the input buffer comprising:

• a driving control unit configured to output an activation control signal;
• a buffer unit coupled to a the driving control unit and configured to compare a voltage of an input signal to a preset reference voltage in response to an activation control signal, and output a result of the comparison as an output signal to an output node;
• and
• a response speed control unit coupled to a buffer unit and configured to include a pulse generating unit configured to receive the input signal and the output signal output from the output node and to generate a pulse signal, wherein the pulse generating unit includes a NOR gate, and a pull-down unit coupled to the pulse generating unit and configured to perform a control operation to change a logic level of a voltage at the output node in response to receiving the pulse signal output by the pulse generating unit, wherein the response speed control unit is configured to activate and output a pulse signal when the input signal changes from a high level to a low level while the output from the output node is a low level or the output from the output node changes from a high level to a low level.