Ultra low power LVDS driver with built in impedance termination to supply and ground rails

A low voltage differential signaling (LVDS) output stage circuit comprising:

• a first supply voltage port for receiving of a first potential;
• a second supply voltage port for receiving of a second potential that is lower than the first potential;
• a differential input port, comprising a first input port and a second input port, for receiving of a differential input signal having transitions between the first and second potentials;
• a follower output stage comprising first and second NMOS pull-up FET devices and first and second PMOS pull-down FET devices disposed between the first and second supply voltage ports for being biased between the first and second potentials;
• a differential output port formed between junctions of the first NMOS pull-up FET device and the first PMOS pull-down FET device and the second NMOS pull-up FET devices and the second PMOS pull-down FET devices for providing of a low voltage differential signal therefrom;
• a first set of coupling capacitors disposed between the first input port and gate terminals of the first NMOS pull-up FET device and the first PMOS pull-down FET device;
• a second set of coupling capacitors disposed between the second input port and gate terminals of the second NMOS pull-up FET device and the second PMOS pull-down FET device;
• and,
• DC restoration circuitry coupled with each of the gate terminals of the FET devices for providing of a DC potential to the first and second sets of coupling capacitors in response to transitions in the differential input signal.

A method comprising:

• AC coupling of a differential input signal to a follower output stage, the AC coupling performed using higher speed lower voltage devices;
• DC restoring of a portion of the differential input signal to the follower output stage, the DC restoring performed using slower higher voltage devices;
• summing the AC coupled differential input signal and the DC bias voltage together in the follower output stage to form a differential output signal;
• and
• level shifting of the differential input signal to form a level shifted differential input signal that is at a higher potential than the differential input signal.

A LVDS output stage circuit comprising:

• means for AC coupling of a differential input signal to a follower output stage, the AC coupling performed using higher speed lower voltage devices;
• means for DC restoring of a portion of the differential input signal to the follower output stage, the DC restoring performed using slower higher voltage devices;
• means for summing the AC coupled differential input signal and the DC bias voltage together in the follower output stage to form a differential output signal;
• and
• means for level shifting the differential input signal to form a level shifted differential input signal that is at a higher potential than the differential input signal.