Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis

A computer readable medium storing a representation of a circuit, the representation comprising:

• a first portion representing a first storage element and a first clock gating element in the circuit, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element in the circuit, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element;
• and
• a second portion representing the CL element in the circuit, wherein the output of the CL element is exclusively sensitized from at least one data input of the CL element by at least one control input of the CL element when each of the at least one control input of the CL element is in a first quiescence inducing condition with respect to the clock signal, wherein each of the at least one control input of the CL element does not change state between previous and current clock periods in the first quiescence inducing condition,
• wherein the first clock gating element is configured to generate the first clock enable signal, using the at least one data input of the CL element, the at least one control input of the CL element, and the clock signal, to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in a second quiescence inducing condition with respect to the clock signal at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition, wherein each of the at least one data input of the CL element does not change state from the previous clock period to the current clock period in the second quiescence inducing condition.

A method to clock-gate a circuit, comprising:

• identifying a first storage element and a combinatorial logic (CL) element in the circuit, wherein the first storage element is clocked by a clock signal, wherein a data input of the first storage element is coupled to an output of the CL element in the circuit;
• identifying a first quiescence inducing condition of at least one control input of the CL element with respect to the clock signal, wherein each of the at least one control input of the CL element does not change state between previous and current clock periods in the first quiescence inducing condition, wherein the output of the CL element is exclusively sensitized from at least one data input of the CL element by the at least one control input of the CL element when each of the at least one control input of the CL element is in the first quiescence inducing condition;
• identifying a second quiescence inducing condition of the at least one data input of the CL element with respect to the clock signal, wherein each of the at least one data input of the CL element does not change state between previous and current clock periods in the second quiescence inducing condition,
• providing a first clock gating element, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element,
• wherein the first clock gating element is configured to generate the first clock enable signal, using the at least one data input of the CL element, the at least one control input of the CL element, and the clock signal, to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in the second quiescence inducing condition at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition.

A computer readable medium storing instructions when executed by a processor comprising functionalities for:

• identifying a first storage element in the circuit, wherein the first storage element is clocked by a clock signal, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element in the circuit;
• identifying a first quiescence inducing condition of the at least one control input of the CL element with respect to the clock signal, wherein each of the at least one control input of the CL element does not change state between previous and current clock periods in the first quiescence inducing condition, wherein the output of the CL element is exclusively sensitized from at least one data input of the CL element by the at least one control input of the CL element when each of the at least one control input of the CL element is in the first quiescence inducing condition;
• identifying a second quiescence inducing condition of at least one data input of the CL element with respect to the clock signal, wherein each of the at least one data input of the CL element does not change state between previous and current clock periods in the second quiescence inducing condition;
• providing a first clock gating element, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element;
• and
• wherein the first clock gating element is configured to generate the first clock enable signal, using the at least one data input of the CL element, the at least one control input of the CL element, and the clock signal, to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in the second quiescence inducing condition at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition.