Circuits for sharing self-timed logic

A circuit, comprising:

• a shared logic circuit having first and second self-timed inputs and first and second self-timed outputs;
• an input circuit having a first self-timed output coupled to the first input of the shared logic circuit, a second self-timed output coupled to the second input of the shared logic circuit, and a self-timed select output;
• an output circuit having a first self-timed input coupled to the first output of the shared logic circuit, a second self-timed input coupled to the second output of the shared logic circuit, a self-timed select input, and first and second self-timed outputs;
• and
• a pipelined routing path routing a self-timed select signal from the select output of the input circuit to the select input of the output circuit;
• wherein the input circuit is coupled to provide a token with one of the first or second outputs based on a value output by an arbitration circuit within the input circuit;
• and
• wherein the output circuit is coupled to provide an output token with one of the first or second outputs based on a value of the self-timed select signal routed from the input circuit through the pipelined routing path.

An integrated circuit, comprising:

• an array of substantially similar programmable logic blocks;
• and
• a interconnect structure interconnecting the programmable logic blocks,
• wherein the array comprises:
• a first group of the logic blocks programmed to implement a shared logic circuit having first and second self-timed inputs and first and second self-timed outputs;
• a second group of the logic blocks programmed to implement an input circuit coupled to output a selected one of the first or second self-timed inputs to the shared logic circuit, the selected one of the first or second inputs being determined by an arbitration circuit within the input circuit, and further to output a self-timed select signal;
• and
• a third group of the logic blocks programmed to implement an output circuit coupled to receive the first and second self-timed outputs from the shared logic circuit and to provide a selected one of the first or second outputs, the selected one of the first or second outputs being determined by the self-timed select signal, and
• wherein the interconnect structure comprises a pipelined routing path routing the self-timed enable signal from the input circuit to the output circuit.