Redundant configuration memory systems and methods

A programmable logic device comprising:

• a plurality of configuration memory cells;
• at least one spare configuration memory cell adapted to store configuration data for a memory cell identified within the plurality of configuration memory cells;
• a plurality of bitlines;
• a plurality of wordlines;
• means for providing programming signals to the plurality of configuration memory cells via the wordlines;
• and
• means for providing configuration data to the plurality of configuration memory cells via the bitlines and for providing configuration data from the spare configuration memory cell to the identified configuration memory cell.

A programmable logic device comprising:

• a plurality of columns of configuration memory cells;
• at least one column of spare configuration memory cells adapted to store configuration data for a memory cell identified within a column of configuration memory cells;
• an address shift register coupled to the columns of configuration memory cells via wordlines and adapted to provide programming signals to the configuration memory cells;
• and
• a data shift register coupled to the columns of configuration memory cells via bitlines and adapted to provide configuration data to the configuration memory cells,
• wherein the data shift register is further coupled to the column of spare configuration memory cells and adapted to provide configuration data from the spare configuration memory cells to a column of configuration memory cells that includes the identified configuration memory cell in response to a programming signal from the address shift register.