Bus-based logic blocks for self-timed integrated circuits

An integrated circuit, comprising:

• an array of logic blocks;
• and
• an interconnect structure interconnecting the logic blocks,
• wherein each logic block comprises:
• N first input multiplexers each having a select input, a plurality of data inputs, and an output, wherein N is an integer greater than one, wherein the select inputs of all N first input multiplexers are coupled one to another;
• wherein a corresponding one of the data inputs of each of the N first input multiplexers comprises a corresponding bit of a first self-timed N-bit bus, the first self-timed N-bit bus being coupled to a first N-bit bus of the interconnect structure;
• N second input multiplexers each having a select input, a plurality of data inputs, and an output, wherein the select inputs of all N second input multiplexers are coupled one to another;
• wherein a corresponding one of the data inputs of each of the N second input multiplexers comprises a corresponding bit of a second self-timed N-bit bus, the second self-timed N-bit bus being coupled to a second N-bit bus of the interconnect structure;
• and
• N first lookup tables, each first lookup table having a first input coupled to the output of a corresponding one of the first input multiplexers, a second input coupled to the output of a corresponding one of the second input multiplexers, a plurality of control inputs, and an output, wherein corresponding control inputs of all N first lookup tables are coupled one to another.

A programmable integrated circuit, comprising:

• an array of programmable logic blocks;
• and
• an interconnect structure interconnecting the programmable logic blocks,
• wherein each programmable logic block comprises:
• N first input multiplexers each having a select input, a plurality of data inputs, and an output, wherein N is an integer greater than one, wherein the select inputs of all N first input multiplexers are coupled one to another;
• wherein a corresponding one of the data inputs of each of the N first input multiplexers comprises a corresponding bit of a first self-timed N-bit bus, the first self-timed N-bit bus being coupled to a first N-bit bus of the interconnect structure;
• N second input multiplexers each having a select input, a plurality of data inputs, and an output, wherein the select inputs of all N second input multiplexers are coupled one to another;
• wherein a corresponding one of the data inputs of each of the N second input multiplexers comprises a corresponding bit of a second self-timed N-bit bus, the second self-timed N-bit bus being coupled to a second N-bit bus of the interconnect structure;
• and
• N first lookup tables, each first lookup table having a first input coupled to the output of a corresponding one of the first input multiplexers, a second input coupled to the output of a corresponding one of the second input multiplexers, a plurality of control inputs, and an output, wherein corresponding control inputs of all N first lookup tables are coupled one to another.