US 7,746,101 B1 · Cascading input structure for logic blocks in integrated circuits

Abstract

A cascading input structure for logic blocks in an integrated circuit. An exemplary integrated circuit includes a plurality of substantially similar logic blocks arrayed to form a column of the logic blocks, and a self-timed vertical cascade chain. Each of the logic blocks has self-timed first and second inputs. The vertical cascade chain has a plurality of self-timed outputs, each of the self-timed outputs being coupled to a first self-timed input of a corresponding logic block in the column. In some embodiments, each logic block includes a multiply block having first and second self-timed inputs, where each output of the vertical cascade chain is coupled to the first input of the multiply block in the corresponding logic block. In some embodiments having a multiply block in the logic block, the inputs and output may not be self-timed.

Claims20

Dependent claims

A logic block, comprising:

a logic circuit having first and second self-timed inputs and a self-timed output;
and
an input circuit, wherein the input circuit comprises:
a first multiplexing circuit having a plurality of self-timed inputs coupled to a plurality of self-timed inputs of the logic block, and further having a self-timed output coupled to the first input of the logic circuit;
and
a second multiplexing circuit having a self-timed first input coupled to a self-timed cascade input of the logic block, a self-timed second input coupled to a self-timed data input of the logic block, and a self-timed output coupled to the second input of the logic circuit,
wherein the output of the second multiplexing circuit is further coupled to a cascade output of the logic block, and
wherein the cascade output of the logic block is coupled to a cascade input of an adjacent logic block.

5 more elements

Dependencies are inferred from the claim text.

Cascading input structure for logic blocks in integrated circuits

Life of this patent

Cascading input structure for logic blocks in integrated circuits

Life of this patent

Abstract

Claims20