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US 7,745,940 B2Granted
Forming ultra dense 3-D interconnect structures
AssigneeIntel Corporation
InventorPatrick R. Morrow
Life of this patent
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Abstract
Methods of forming a microelectronic structure are described. Embodiments of those methods include bonding at least one bond pad of a device side of a first substrate to at least one bond pad of a device side of a second substrate, forming at least one via to connect to at least one of an active feature and an interconnect structure disposed within the first substrate, and forming a reactive material on a surface of at least one of the active features.
Claims8
A structure comprising:
- at least one bond pad of a device side of a first substrate coupled to at least one bond pad of a device side of a second substrate, wherein the second substrate comprises at least one of a gate and a source/drain;
- a via extending through the non-device side of the first substrate and disposed directly on a second side of a gate and a source/drain disposed within the first substrate, wherein the via comprises a dielectric lining on an inner portion of the via;
- and
- a silicide confined within the via on the second side of the one of the gate and the source/drain.
1 more element
Dependencies are inferred from the claim text.