Semiconductor package, semiconductor package module including the semiconductor package, and methods of fabricating the same

A semiconductor package module comprising:

• a module substrate;
• a first semiconductor package mounted on the module substrate, the first semiconductor package comprising:
• a leadframe including a leadframe substrate having first and second major surfaces;
• a first group of semiconductor chips stacked and mounted on the first major surface of the leadframe substrate, the width of the semiconductor chips of the first group taken along a first direction parallel to the first major surface being less than a width of the first major surface taken along the first direction, each of the first group of semiconductor chips having same functional chip pads, the first group of semiconductor chips comprising at least four semiconductor chips;
• a second group of semiconductor chips stacked and mounted on the second major surface of the leadframe substrate, the width of the semiconductor chips of the second group taken along the first direction parallel to the second major surface being less than a width of the second major surface taken along the first direction, each of the second group of semiconductor chips having same functional chip pads, the second group of semiconductor chips comprising at least four semiconductor chips;
• a first group of pins adjacent to one side of the leadframe substrate and having no direct electrical connection with the leadframe substrate;
• a second group of pins adjacent to an opposite side of the one side of the leadframe substrate and having no direct electrical connection with the leadframe substrate, the first group of pins being line symmetric with the second group of pins with respect to a line having a second direction which is perpendicular to the first direction, and each pin of the first group of pins being line symmetric with a corresponding pin of the second group of pins having a same function with the corresponding pin of the second group of pins;
• a first group of wires connected between the chip pads of the first group of semiconductor chips and the first group of pins, chip pads of the first group of semiconductor chips having a same function and same relative location being connected to a same pin of the first group of pins;
• a second group of wires connected between the chip pads of the second group of semiconductor chips and the second group of pins, chip pads of the second group of semiconductor chips having a same function and same relative location being connected to a same pin of the second group of pins;
• and
• an encapsulant encapsulating the leadframe substrate and the semiconductor chips;
• a first wiring formed on the module substrate connected to an I/O pin of the first group of pins and an I/O pin of the second group of pins, functions of the I/O pin of the first group of pins and the I/O pin of the second group of pins being the same and the locations of the I/O pin of the first group of pins and the I/O pin of the second group of pins being line symmetric with respect to the line having a second direction which is perpendicular to the first direction;
• and
• a second wiring formed on the module substrate connected to a pin of the first group of pins and not connected to any of the second group of pins.

A semiconductor package comprising:

• a first chip group comprising a first semiconductor chip and a second semiconductor chip;
• a second chip group comprising a third semiconductor chip and a fourth semiconductor chip;
• a first set of package terminals, each of the first set of package terminals having an electrical connection to a pad of the first semiconductor chip and a pad of the second semiconductor chip which have a same function;
• a second set of package terminals, each of the second set of package terminals having an electrical connection to a pad of the third semiconductor chip and a pad of the fourth semiconductor chip which have a same function;
• a first chip enable package terminal electrically connected to a chip enable pad of the first semiconductor chip to provide access to the first semiconductor chip;
• a second chip enable package terminal electrically connected to a chip enable pad of the second semiconductor chip to provide access to the second semiconductor chip;
• a third chip enable package terminal electrically connected to a chip enable pad of the third semiconductor chip to provide access to the third semiconductor chip;
• a fourth chip enable package terminal electrically connected to a chip enable pad of the fourth semiconductor chip to provide to access the fourth semiconductor chip.

A semiconductor package comprising:

• a first chip group comprising a plurality of semiconductor chips;
• a second chip group comprising a plurality of semiconductor chips;
• first package terminals;
• second package terminals;
• each of the semiconductor chips including chip pads to receive at least one of signals and external power supply voltages,
• wherein all semiconductor chips of the first chip group share first package terminals, chip pads of each of the semiconductor chips of the first group having signal or external power supply connections to respective same terminals of the first package terminals;
• wherein all semiconductor chips of the second chip group share second package terminals, chip pads of each of the semiconductor chips of the second group having signal or external power supply connections to respective same terminals of the second package terminals;
• wherein the first package terminals are electrically unconnected to the second package terminals within the semiconductor package;
• wherein at least some of the chip pads of semiconductor chips of the first chip group are not electrically connected within the package to chip pads of other semiconductor chips of the first chip group;
• and
• wherein at least some of the chip pads of semiconductor chips of the second chip group are not electrically connected within the package to chip pads of other semiconductor chips of the second chip group.