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US 7,745,919 B2Granted
Semiconductor device including a plurality of semiconductor chips and a plurality of through-line groups
AssigneeElpida Memory, Inc.
InventorsKayoko Shibata, Hiroaki Ikeda
Life of this patent
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Abstract
A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.
Claims6
A semiconductor device comprising:
- a plurality of semiconductor chips, each of which includes:
- lower and upper surfaces;
- a plurality of lower terminals on the lower surface;
- a plurality of upper terminals on the upper surface, each of the upper terminals being vertically aligned correspondingly with one of the lower terminals;
- and
- a plurality of conductive lines, each of the conductive lines being provided to electrically connect an associated one of the lower terminals to an associated one of the upper terminals which is not vertically aligned to the associated one of the lower terminals, wherein
- the plurality of the semiconductor chips are stacked with each other such that the upper terminals of a lower one of the semiconductor chips are connected respectively to the lower terminals of an upper one of the semiconductor chips, and
- each of the lower electrodes of the lowermost semiconductor chip is electrically connected through the conductive lines to, and vertically aligned with, a corresponding one of the upper terminals of the uppermost semiconductor chip.
5 more elements
A semiconductor device comprising:
- a plurality of semiconductor chips, each of the chips including:
- lower and upper surfaces;
- a plurality of lower terminals provided apart from each other on the lower surface, the lower terminals including a first lower terminal;
- a plurality of upper terminals provided apart from each other on the upper surface, the upper terminals including a first upper terminal that is vertically aligned with the first lower terminal;
- and
- a plurality of conductive lines, each of the conductive lines being provided to electrically connect an associated one of the lower terminals including the first lower terminal to an associated one of the upper terminals including the first upper terminal, the associated ones of the lower and upper terminals to be electrically connected to each other by one of conductive line being not vertically aligned with each other, wherein
- the plurality of semiconductor chips are stacked with each other such that the upper terminals of a lower one of the semiconductor chips are connected to the lower terminals of an upper one of the semiconductor chips, and
- the first lower terminal of the lowermost semiconductor chip is vertically aligned with, and electrically connected through at least one intermediate semiconductor chip between the lowermost and uppermost semiconductor chips to, the first upper terminal of an uppermost semiconductor chip.
5 more elements
Dependencies are inferred from the claim text.