Semiconductor integrated circuit devices including gate patterns having step difference therebetween and a connection line disposed between the gate patterns and methods of fabricating the same

A semiconductor IC device comprising:

• a semiconductor substrate including a peripheral circuit region and a cell array region, the cell array region comprising a cell edge region and a cell central region, the cell central region substantially surrounded by the cell edge region, and the cell edge region substantially surrounded by the peripheral circuit region;
• a device isolation layer disposed in the peripheral circuit region, the cell edge region and the cell central region, the device isolation layer defining a cell active region in the cell central region and a peripheral active region in the peripheral circuit region;
• a peripheral gate pattern disposed on the peripheral active region of the peripheral circuit region and extending upward from a top surface of the peripheral active region;
• cell gate patterns disposed in the cell active region of the cell central region and the device isolation layer of the cell edge region and protruding into the cell active region and the device isolation layer;
• and
• a connection line contacting the cell gate pattern and the device isolation layer of the cell edge region,
• wherein each of the cell gate patterns comprises a cell gate and a cell gate capping pattern which are sequentially stacked, the cell gate patterns contact each other through the device isolation layer, and the connection line contacts the cell gate and the device isolation layer,
• wherein the connection line has a substantially uniform width on the cell gate and extends into the semiconductor substrate so as to substantially surround the cell gate.