Differential negative resistance memory
AssigneeMicron Technology, Inc.
InventorKristy A. Campbell
Life of this patent
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Abstract
The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes and to methods of making such a device. The stored data is semi-volatile. Generally, information written to a device in accordance with the invention can maintain its memory for a matter of minutes, hours, or days before a refresh is necessary. The power requirements of the device are far reduced compared to DRAM. The memory function of the device is highly stable, repeatable, and predictable. The device can be produced in a variety of ways.
Claims11
A differential negative resistance memory device, comprising:
- a substrate;
- a first conductive layer over said substrate;
- a first germanium selenide layer over said first conductive layer;
- a silver selenide layer over said first germanium selenide layer;
- a second germanium selenide layer over said silver selenide layer, wherein said first and second germanium selenide layers have a chemical formula GexSe100-x, x being in the range of about 18-43;
- a silver layer over said second germanium selenide layer;
- and
- a second conductive layer over said silver layer;
- wherein at least said first germanium selenide layer is configured to exhibit a differential negative resistance memory such that it is programmable to a higher current flow read state and a lower current flow read state in response to applied first and second programming voltages, respectively.
A processor system, comprising;
- a processor;
- a differential negative resistance memory device, said memory device comprising;
- a first electrode and a second electrode;
- and
- a resistance variable region separating said first and second electrodes and in electrical communication therewith, said resistance variable region being configured so as to exhibit differential negative resistance memory behavior as storing at least one memory state as a read current in response to an applied voltage.
Dependencies are inferred from the claim text.