Method of optimizing sidewall spacer size for silicide proximity with in-situ clean

A method comprising sequentially:

• forming a gate of a semiconductor device on a substrate;
• forming sidewall spacers, having a first size, on sides of the gate;
• transporting the substrate to a process module;
• reducing the size of the sidewall spacers from the first size to a second size within the process module;
• pre-cleaning the gate and the substrate within the process module;
• and
• forming silicide regions in the substrate,
• wherein the sidewall spacers having the second size are used to define edges of the silicide regions, and
• wherein reducing the size of the sidewall spacers and pre-cleaning are performed in a continuous vacuum in the process module.

A method comprising:

• forming a gate of an NMOSFET semiconductor device on a substrate;
• etching sidewall spacers on sides of the gate to provide a proximity value, which is defined as a distance between the gate and an edge of a performance-enhancing region, wherein the sidewall spacers are used to define the edge of the region during formation of the region in the substrate;
• and
• pre-cleaning the gate and the substrate in preparation for formation of the region, wherein the etching and the pre-cleaning are performed in a continuous vacuum, the method further comprising:
• forming an additional gate of a PMOSFET device on the substrate;
• and
• patterning a photoresist material over the PMOSFET device prior to etching of the sidewall spacers of the gate of the NMOSFET device,
• wherein the photoresist material is over the PMOSFET device during etching of the sidewall spacers of the gate of the NMOSFET device.

A method comprising:

• forming a gate of an NMOSFET semiconductor device on a substrate;
• reducing sizes of sidewall spacers on sides of the gate within a process module;
• performing a pre-silicide clean of the gate and the substrate within the process module;
• and
• forming silicide regions in the substrate,
• wherein the sidewall spacers are used to define edges of the silicide regions, and wherein the reducing of sizes of the sidewall spacers and the performing of the pre-silicide clean are performed in a continuous vacuum in the process module, the method further comprising:
• forming an additional gate of a PMOSFET device on the substrate;
• and
• patterning a photoresist material over the PMOSFET device prior to the reducing of the sizes of sidewall spacers of the gate of the NMOSFET device,
• wherein the photoresist material is over the PMOSFET device during the reducing of the sizes of the sidewall spacers of the gate of the NMOSFET device.