Method for reducing silicide defects in integrated circuits

A method for reducing metal pipes comprising:

• providing a feature on a substrate;
• forming dielectric spacers on sidewalls of the feature;
• forming metal silicide contacts on the substrate adjacent to the dielectric spacers, wherein portions of the metal silicide contacts are covered by the spacers;
• and
• pulling back the dielectric spacers, wherein outer walls of the dielectric spacers are aligned with edges of the metal silicide contacts, wherein aligning the edges of the dielectric spacers and metal silicide contacts reduces formation of metal pipes.

A method of fabricating an integrated circuit comprising:

• providing a semiconductor body having STI, gate and spacer structures;
• forming a Ni or NiPt layer over the structures;
• forming TiN cap layer over the structures;
• forming first phase Ni silicide layer via RIA1 at 300-400° C., wherein portions of the Ni silicide layer are covered by the spacers;
• performing wet clean to remove the TiN cap and unreacted Ni;
• dry (plasma) etching of the spacer to have spacer pull-back, wherein outer walls of the spacers are aligned with edges of the Ni silicide contacts;
• and
• forming second phase Ni silicide layer via RTA2 at 400-600° C.