Method of forming a FET having ultra-low on-resistance and low gate charge

A method of forming a field effect transistor, comprising:

• providing a substrate of a first conductivity type silicon;
• forming a substrate cap region of the first conductivity type silicon such that a junction is formed between the substrate cap region and the substrate;
• forming an epitaxial layer of the first conductivity type silicon over the substrate cap region;
• implanting dopants of a second conductivity type into the epitaxial layer and driving the dopants into the epitaxial layer to thereby form a body region having a junction with the substrate cap region;
• forming a plurality of trenches each extending at least through the body region;
• lining the sidewalls and bottom of each trench with a dielectric material;
• at least partially filling each trench with a conductive material;
• and
• forming a plurality of source regions of the first conductivity type in an upper portion of the body region,
• wherein during one or more temperature cycles, dopants of the first conductivity type in the substrate cap region out-diffuse into a lower portion of the body region to form an out-diffusion region of the first conductivity type extending from the junction between the body region and the substrate cap region into the body region such that a spacing between the source regions and the out-diffusion region defines a length of a channel region of the field effect transistor.

A field effect transistor, comprising:

• a substrate of a first conductivity type silicon;
• an epitaxial substrate cap region of the first conductivity type silicon over and in contact with the substrate;
• an epitaxial body region of a second conductivity type over and in contact with the substrate cap region;
• a plurality of trenches each extending at least through the body region;
• a dielectric material lining the sidewalls and bottom of each trench;
• a conductive material at least partially filling each trench;
• a plurality of source regions of the first conductivity type in an upper portion of the body region;
• and
• an out-diffusion region of the first conductivity type extending from an interface between the body region and the substrate cap region into the body region such that a spacing between each source region and the out-diffusion region defines a length of a channel region of the field effect transistor, the channel region extending vertically along a sidewall of each trench.