Gate self aligned low noise JFET

A method of forming a junction field effect transistor (JFET), comprising:

• forming a bottom gate region having a first electrical conductivity type in a semiconductor substrate;
• forming an epitaxial layer having a second electrical conductivity type over the semiconductor substrate;
• forming first and second well regions having the first electrical conductivity type at spaced apart locations in the epitaxial layer down to the bottom gate region;
• forming a layer of gate dielectric material over the epitaxial layer;
• forming a layer of gate electrode material over the layer of gate dielectric material;
• patterning the layer of gate electrode material to form first and second patterned gate electrode material structures over the epitaxial layer over the bottom gate region, between the first and second well regions;
• forming sidewall spacers on sides of the first and second patterned gate electrode material structures;
• forming a top gate region having the first electrical conductivity type in the epitaxial layer over the bottom gate region, between facing ones of the sidewall spacers of the first and second patterned gate electrode material structures;
• and
• forming a source region having the second electrical conductivity type in the epitaxial layer over the bottom gate region, between a non-facing one of the sidewall spacers of the first patterned gate electrode material structure and the first well region;
• and
• forming a drain region having the second electrical conductivity type in the epitaxial layer over the bottom gate region, between a non-facing one of the sidewall spacers of the second patterned gate electrode material structure and the second well region.