Semiconductor chip with stratified underfill

An apparatus, comprising:

• a semiconductor chip coupled to a substrate;
• and
• an underfill layer between the semiconductor chip and the substrate, the underfill layer including a first plurality of filler particles having a first average density and a second plurality of filler particles having a second average density lower than the first average density such that the first plurality of filler particles being concentrated proximate the substrate and the second plurality of filler particles being concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer being larger proximate the substrate than proximate the semiconductor chip.

A method of manufacturing, comprising:

• coupling a semiconductor chip to a substrate to leave a gap therebetween;
• and
• forming an underfill layer in the gap, the underfill layer including a first portion proximate the substrate that has a first coefficient of thermal expansion and a majority concentration of first filler particles with a first average size, and a second portion proximate the semiconductor chip that has a second coefficient of thermal expansion greater than the first coefficient of thermal expansion and a majority concentration of second filler particles with a second average size smaller than the first average size.

An apparatus, comprising:

• a semiconductor chip coupled to a substrate;
• and
• an underfill layer between the semiconductor chip and the substrate, the underfill layer including a first portion proximate the substrate that has a first coefficient of thermal expansion and a majority concentration of first filler particles with a first average size, and a second portion proximate the semiconductor chip that has a second coefficient of thermal expansion greater than the first coefficient of thermal expansion and a majority concentration of second filler particles with a second average size smaller than the first average size.