Method of forming semiconductor package

A method of forming a plurality of semiconductor packages, comprising:

• forming a plurality of cavities in a substrate;
• forming an electrically conductive pattern on the substrate and atop the cavities;
• forming an electrically insulating layer over the substrate and the electrically conductive pattern;
• forming a plurality of vias in the electrically insulating layer;
• attaching a plurality of integrated circuit (IC) dice to the electrically insulating layer;
• electrically connecting the IC dice to the vias, thereby connecting the IC dice to the electrically conductive pattern;
• performing a molding operation to encapsulate the IC dice;
• and
• removing the substrate, thereby exposing the electrically conductive pattern.

A method of forming a semiconductor package, comprising:

• forming a plurality of cavities in a substrate;
• forming an electrically conductive pattern on the substrate and over the cavities;
• forming an electrically insulating layer over the substrate and the electrically conductive pattern;
• forming a plurality of through-holes through the electrically insulating layer to the electrically conductive pattern;
• plating the through-holes with an electrically conductive material to form a plurality of vias in the electrically insulating layer;
• attaching an integrated circuit (IC) die to the electrically insulating layer;
• electrically connecting the IC die to the vias with a plurality of bonding wires, thereby connecting the IC die to the electrically conductive pattern;
• performing a molding operation to encapsulate the IC die and the bonding wires;
• and
• removing the substrate, thereby exposing the electrically conductive pattern.