Layered chip package and method of manufacturing same

A method of manufacturing a layered chip package, the layered chip package comprising:

• a main body having a top surface, a bottom surface and four side surfaces;
• wiring disposed on at least one of the side surfaces of the main body;
• a plurality of first terminals disposed on the top surface of the main body;
• and
• a plurality of second terminals disposed on the bottom surface of the main body, wherein:
• the main body includes a plurality of layer portions stacked;
• each of the plurality of layer portions includes:
• a semiconductor chip having a top surface, a bottom surface and four side surfaces;
• an insulating portion covering at least one of the four side surfaces of the semiconductor chip;
• and a plurality of electrodes connected to the semiconductor chip;
• the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed;
• each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed;
• and
• the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals,
• the method comprising the steps of:
• fabricating a plurality of substructures that respectively correspond to the plurality of layer portions of the layered chip package, each substructure including a plurality of its corresponding layer portions and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions;
• and
• completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the first terminals, the second terminals and the wiring on the main body.

An electronic component comprising a plurality of layered chip packages and formed by electrically connecting every vertically adjacent two of the layered chip packages to each other,

• each of the plurality of layered chip packages comprising:
• a main body having a top surface, a bottom surface and four side surfaces;
• wiring disposed on at least one of the side surfaces of the main body;
• a plurality of first terminals disposed on the top surface of the main body;
• and
• a plurality of second terminals disposed on the bottom surface of the main body, wherein:
• the main body includes a plurality of layer portions stacked between the top surface and the bottom surface;
• each of the plurality of layer portions includes:
• a semiconductor chip having a top surface, a bottom surface and four side surfaces;
• an insulating portion covering at least one of the four side surfaces of the semiconductor chip;
• and a plurality of electrodes connected to the semiconductor chip;
• the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed;
• each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed;
• the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals;
• and
• in the vertically adjacent two of the layered chip packages, the first terminals of the lower one of the layered chip packages are electrically connected to the second terminals of the upper one of the layered chip packages.