High voltage power supply clamp circuitry for electrostatic discharge (ESD) protection

A circuit for protecting against ESD, the circuit comprising:

• a switchable current sink comprising a plurality of transistors coupled in series, wherein the switchable current sink is coupled to a positive ESD clamp rail;
• a control circuit coupled to a control connection of the switchable current sink, the control circuit configured to couple, without an appreciable voltage drop, the control connection to a negative ESD clamp rail when an ESD event occurs on the positive ESD clamp rail;
• and
• a voltage divider circuit coupled to the switchable current sink for dividing down a voltage seen at the positive ESD clamp rail;
• wherein the control circuit comprises a gate drive circuit coupled to a respective gate of each of the plurality of transistors coupled in series, wherein the gate drive circuit is configured to couple each respective gate to the negative ESD clamp rail during the ESD event;
• wherein the gate drive circuit comprises:
• a pull down circuit;
• a trigger circuit coupled to the pull down circuit;
• and
• a level shifting inverter having a supply terminal coupled to the positive ESD clamp rail voltage and a reference terminal coupled to the negative ESD clamp rail voltage, the level shifting inverter coupled to the trigger circuit and to the pull down circuit, wherein the level shifting inverter is configured to turn on the switchable current sink via the pull down circuit during the ESD event, the pull down circuit thereby coupling each respective gate to the negative ESD clamp rail during the ESD event.

A protection circuit for protecting against electrostatic discharge (ESD), the protection circuit comprising:

• a switchable current sink having a first control node and a second control node, and providing a discharge path between a positive ESD clamp rail and a negative ESD clamp rail, the discharge path capable of sinking substantially large currents when activated;
• a transistor device having a channel coupled between the first control node and the negative ESD clamp rail, wherein the transistor device couples the first control node to the negative ESD clamp rail when turned on, to activate the switchable current sink;
• a first control circuit coupled between the positive ESD clamp rail and the first control node, and further coupled to an internal control node, wherein the first control circuit develops a first voltage level at the internal control node in response to a rapidly rising voltage on the positive ESD clamp rail;
• a second control circuit coupled between the positive ESD clamp rail and the first control node, and further coupled to the internal control node and the second control node, wherein the second control circuit couples the first control node to the second control node when the internal control node reaches the first voltage level;
• and
• a third control circuit coupled between the positive ESD clamp rail and the negative ESD clamp rail, and further coupled to the first control node, the second control node, and a control terminal of the transistor device, wherein the third control circuit turns on the transistor device when the first control node is coupled to the second control node, wherein a voltage drop across the channel of the transistor device when the transistor device is turned on is less than a threshold voltage of the transistor device.

A method for protecting a system against electrostatic discharge (ESD) event on a power supply rail used to provide power to the system, the method comprising:

• developing a stable voltage level at a first control node of a switchable current sink, wherein the stable voltage level is a mid-level voltage between a voltage level of the power supply rail and a voltage reference rail;
• developing a first voltage level at an internal control node in response to a rapidly rising voltage on the power supply rail;
• pulling a second control node of the switchable current sink to the stable voltage level in response to said developing the first voltage level;
• turning on a first transistor device in response to said pulling the second control node to the stable voltage level;
• the first transistor device pulling the first control node and the second control node to the voltage reference rail in response to said turning on the transistor device;
• and
• the switchable current sink providing a discharge path between the power supply rail and the voltage reference rail in response to said pulling the first control node and the second control node to the voltage reference rail.

An ESD protection circuit comprising:

• a switchable current sink having a first and a second control node, and comprising a plurality of transistors coupled in series, wherein the switchable current sink is coupled to a power supply rail, and wherein the first control node resides at a mid-level voltage between a voltage level of the power supply rail and a voltage reference rail during normal operation;
• and
• a control circuit coupled to the first control node and the second control node, and configured to:
• develop a first voltage level at an internal control node in response to a rapidly rising voltage on the power supply rail;
• pull the second control node to the stable voltage level in response to the first voltage level developed at the internal node;
• and
• turn on a first transistor device in response to the second control node being pulled to the stable voltage level, the first transistor device in turn pulling the first control node and the second control node to the voltage reference;
• wherein the switchable current sink is configured to provide a discharge path between the power supply rail and the voltage reference rail in response to the first control node and the second control node of the switchable current sink being pulled to the voltage reference rail.