Semiconductor device structure for anti-fuse
AssigneeApplied Intellectual Properties Co., Ltd.
InventorYuan-Feng Chen
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Abstract
The present invention discloses a semiconductor device, the device comprising a semiconductor layer on a substrate. A gate oxide and a gate electrode are formed on the semiconductor substrate. A gate conductive layer is formed on the gate electrode. A first doped region is formed in the semiconductor layer. A dielectric spacer is optionally formed onto the sidewall of the gate electrode and part of the semiconductor layer. A second doped region is formed from a predetermined distance to the gate electrode, wherein the predetermined distance is no less than the distance between the first doped region and the gate electrode. A third doped region is formed adjacent to the first doped region in the semiconductor layer and between the first doped region and the second doped region.
Claims31
An anti-fuse, comprising:
- a semiconductor substrate;
- a gate dielectric layer formed on said semiconductor substrate;
- a gate electrode formed on said gate dielectric layer;
- a first doped region formed in said semiconductor substrate;
- a second doped region formed from a predetermined distance to said gate electrode, wherein said predetermined distance is larger than the distance between said first doped region and gate electrode and the coupling capacitance formed between said second doped region and said gate electrode is less than the coupling capacitance formed between said first doped region and said gate electrode;
- a metal-semiconductor compound formed on at least one of said gate electrode and said first and second doped regions;
- a conductive plug formed onto said metal-semiconductor compound;
- an isolation layer formed between said gate electrode and said conductive plug;
- and
- a resistance formed between said first and second doped regions wherein said resistance can be alternated by a predetermined electric signal.
An anti-fuse, comprising:
- a semiconductor substrate:
- a gate dielectric layer formed on said semiconductor substrate;
- a gate electrode formed on said gate dielectric layer;
- a first doped region formed in said semiconductor substrate;
- a dielectric spacer formed onto the sidewall of said gate electrode and part of said semiconductor substrate;
- a second doped region formed from a predetermined distance to said gate electrode wherein said predetermined distance is larger than the distance between said first doped region and said gate electrode and the coupling capacitance formed between said second doped region and said gate electrode is less than the coupling capacitance formed between said first doped region and said gate electrode;
- a metal-semiconductor compound formed on at least one of said gate electrode and said first and second doped regions;
- a conductive plug formed onto said metal-semiconductor compound;
- an isolation layer formed between said gate electrode and said conductive plug;
- and
- a resistance formed between said first and second doped regions wherein said resistance can be alternated by a predetermined electric signal.
Dependencies are inferred from the claim text.