Semiconductor integrated circuit including metal mesh structure
AssigneeST-Ericsson SA
InventorAugusto M. Marques
Life of this patent
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Abstract
A metal mesh structure for use in an integrated circuit is described. In one embodiment, a semiconductor integrated circuit includes a first region including, for example, a device layer having one or more active semiconductor devices. The circuit also includes a second region, which may include a metalization layer including circuit wires. The circuit further includes a layer of metal mesh interposed between the first and second regions, and which may be implemented on at least a portion of another metalization layer.
Claims32
A semiconductor integrated circuit die incorporating a plurality of devices, the semiconductor integrated circuit die comprising:
- a first region;
- a second region;
- and
- a plurality of metal layers each providing interconnects for the devices in the first region below the second region, at least a first of the metal layers interposed between the first and second regions and including at least one interconnected metal mesh region formed by a plurality of openings, the at least one interconnected metal mesh region providing shielding between the first and second regions, wherein the at least one metal mesh layer is arranged above the devices.
A semiconductor integrated circuit die incorporating a plurality of devices, the semiconductor integrated circuit die comprising:
- a first region;
- a second region;
- and
- a plurality of metal layers each providing interconnects for the devices in the first region below the second region, at least a first of the metals layers incorporating a shield situated between the first region and the second region, wherein the shield is formed by the metallic layer including an interconnected pattern of substantially uniformly space openings, wherein the shield is arranged above the devices.
An integrated circuit die incorporating a plurality of devices, the integrated circuit die comprising:
- a first signal node;
- a second signal node;
- and
- a plurality of metal layers each providing interconnects for the devices in the second signal node, at least one of the metal layers incorporating an interconnected metallic mesh structure formed between the first and second signal nodes and above the devices.
A method comprising:
- providing a first region of a semiconductor integrated circuit die;
- providing a second region of the semiconductor integrated circuit die;
- providing a plurality of metal layers each providing interconnects for devices in the first region below the second region incorporated into the semiconductor integrated circuit die at least a first one of the metal layers being interposed between the first and second regions;
- and
- incorporating an interconnected metal mesh in the first metal layer between the first and second regions, wherein the metal mesh is arranged above the devices.
Dependencies are inferred from the claim text.