Semiconductor device, method of manufacturing same and method of designing same

A semiconductor device having an SOI structure including a substrate, an insulation layer over said substrate and a silicon layer over said insulation layer, comprising:

• a first well region having n-type conductivity type and a second well region having p-type conductivity type both formed in said silicon layer;
• a first insulating film formed in said silicon layer between said first well region and said second well region, and said first insulating film contacts said first well region, said second well region and said insulation layer;
• PMOS transistors each having a first gate electrode over a surface of said silicon layer, a p-type source region and a p-type drain region formed in said silicon layer at both sides of said first gate electrode, and an n-type channel forming region forming region being between said p-type source region and said p-type drain region;
• a second insulating film formed in said silicon layer and being between said PMOS transistors;
• NMOS transistors each having a second gate electrode over a surface of said silicon layer, an n-type source region and an n-type drain region formed in said silicon layer at both sides of said second gate electrode, and a p-type channel forming region being between said n-type source region and said n-type drain region;
• and
• a third insulating film formed in said silicon layer and being between said NMOS transistors,
• wherein said p-type source and p-type drain regions of said PMOS transistors and said n-type source and n-type drain regions of said NMOS transistors respectively have depths which satisfy the condition that each of depletion layers extending from said respective p-type and n-type source/drain regions reach said insulation layer in a built-in state.

A semiconductor device having an SOI structure including a substrate, an insulation layer over said substrate and a silicon layer over said insulation layer, comprising:

• a first well region having n-type conductivity type and a second well region having p-type conductivity type both formed in said silicon layer;
• a first insulating film formed in said silicon layer between said first well region and said second well region, and said first insulating film contacts said first well region, said second well region and said insulation layer;
• PMOS transistors formed in said first well region and each having a first gate electrode over a surface of said silicon layer, a p-type source region and a p-type drain region formed in said first well region at both sides of said first gate electrode, and an n-type channel forming region being between said p-type source region and said p-type drain region;
• a second insulating film formed in said first well region and being between said PMOS transistors;
• a first body region having n-type conductivity type formed in said first well region;
• a first connecting region having n-type conductivity type being between said n-type channel forming region and said first body region;
• a third insulating film formed in said first well region and being between said n-type channel forming region and said first body region, and said third insulating film formed over said first connecting region;
• NMOS transistors formed in said second well region and each having a second gate electrode over a surface of said silicon layer, an n-type source region and an n-type drain region formed in said silicon layer at both sides of said second gate electrode, and a p-type channel forming region being between said n-type source region and said n-type drain region;
• a fourth insulating film formed in said second well region and being between said NMOS transistors;
• a second body region having p-type conductivity type formed in said second well region;
• a second connecting region having p-type conductivity type being between said p-type channel forming region and said second body region;
• and
• a fifth insulating film formed in said second well region and being between said p-type channel forming region and said second body region, and said fifth insulating film formed over said second connecting region,
• wherein said p-type source and p-type drain regions of said PMOS transistors and said n-type source and n-type drain regions of said NMOS transistors respectively have depths which satisfy the condition that each of depletion layers extending from said respective p-type and n-type source/drain regions reach said insulation layer in a built-in state.