Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics

A method of forming an interconnect structure for an integrated circuit, comprising the steps of:

• providing a substrate;
• forming a dielectric stack on said substrate comprising an etch-stop layer, a low-k dielectric layer on said etch-stop layer, and a hardmask layer on said low-k dielectric layer;
• patterning a photoresist masking layer on said dielectric stack to define a plurality of feature defining regions;
• plasma processing said substrate in a plasma-based reactor, said processing comprising etching a plurality of features into said hardmask layer and into at least a portion of said low-k dielectric layer in said feature defining regions, performing a plasma ash process in situ in said plasma-based reactor, and performing a plasma repair process in situ in said plasma-based reactor, said plasma repair process comprising flowing at least one hydrocarbon into said reactor and generating a plasma, wherein a mass flow rate of said hydrocarbon into said plasma based reactor is at least 0.1 sccm;
• and
• forming a metal conductor in said plurality of features.

A method of forming an interconnect structure in an integrated circuit, comprising the steps of:

• providing a substrate;
• forming a dielectric stack on said substrate comprising an etch-stop layer, a low-k dielectric layer on said etch-stop layer, and a hardmask layer on said low-k dielectric layer;
• patterning a photoresist masking layer on said dielectric stack to define a plurality of feature defining regions;
• processing said substrate in a plasma-based reactor, said processing comprising etching a plurality of features into said hardmask layer and into at least a portion of said low-k layer dielectric layer in said feature defining regions, wherein said first plasma etch process preferentially etches said low-k dielectric layer over said etch-stop layer, performing a first in situ plasma ash process in said plasma-based reactor, again etching said plurality of features into a remaining portion of said low-k layer dielectric layer stack and said etch-stop layer, performing an in situ plasma treatment process in said plasma-based reactor, said plasma repair process comprising flowing at least one hydrocarbon into said reactor and generating a plasma, wherein a mass flow rate of said hydrocarbon into said plasma based reactor is at least 0.1 sccm, and performing a second in situ plasma ash process in said plasma-based reactor;
• removing a residual portion of the patterned masking layer from said substrate;
• and
• forming a metal conductor in the plurality of features.

A method for manufacturing an integrated circuit including a damascene metallization process, comprising:

• providing a substrate having a metal conductor disposed in a first dielectric layer for providing electrical connection to an active device;
• forming an etch-stop layer over the first dielectric layer and the metal conductor;
• forming a second dielectric layer over the etch-stop layer;
• forming a mask over the second dielectric layer;
• patterning the mask;
• performing a plasma etch through the patterned mask to form an opening in the second dielectric layer;
• following the plasma etch, performing an in situ plasma ash to remove etch residue from exposed portions of the second dielectric layer;
• following the plasma etch, and before or after the plasma ash, performing an in situ plasma treatment with an activated hydrocarbon species to repair exposed portions of the second dielectric layer;
• and
• following the plasma ash, performing a wet clean to remove remaining etch residue.