Integrated circuit having a top side wafer contact and a method of manufacture therefor

A method of manufacturing an integrated circuit, comprising:

• forming a first dielectric layer over a doped silicon wafer substrate;
• forming a silicon semiconductor substrate over the first dielectric layer;
• forming a transistor device on or in the semiconductor substrate;
• forming one or more second dielectric layers over the transistor device;
• forming a copper metal feature positioned over the one or more second dielectric layers;
• forming a protective overcoat over the one or more second dielectric layers and over the metal feature;
• forming a hard mask layer over the protective overcoat;
• patterning the hard mask layer;
• forming a trench by etching the protective overcoat, and the one or more second dielectric layers, through the patterned hard mask layer;
• extending the trench through the semiconductor substrate and the first dielectric layer;
• patterning and etching the protective overcoat to form an opening to expose the metal feature;
• forming a seeding layer over the protective overcoat and within the trench and the opening;
• masking the seeding layer to cover the protective overcoat and leave the trench and the opening exposed;
• and
• forming copper conductive plugs within the trench and within the opening, through the masked intermediate layer.