Lateral junction varactor with large tuning range
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorManju Sarkar
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AssigneeChartered Semiconductor Manufacturing Ltd.
InventorManju Sarkar
Estimating the term…
Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly. Thus, tuning range Cmax/Cmin is significantly increased. Tuning range with this configuration can be increased infinitely by increasing the horizontal lengths of the second and third diffusion regions.
A method of forming a junction varactor comprising:
A method of forming a semiconductor device comprising:
Dependencies are inferred from the claim text.