US 7,741,182 B2 · Method of fabricating a dual gate FET

Abstract

The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion (2) on a substrate (1), a first layer (3) and a second layer (4) are formed, after which the top surface of the protrusion (2) is exposed. A portion of the first layer (3) is selectively removed relative to the protrusion (2) and the second layer (4), thereby creating a fin (6) and a trench (5). Also a method is presented to form a plurality of fins (6) and trenches (5). The dual-gate FET is created by forming a gate electrode (7) in the trench(es) (5) and a source and drain region. Further a method is presented to fabricate an extremely short-length asymmetric dual-gate FET with two gate electrodes that can be biased separately.

Claims17

Dependent claims

A method for fabricating a dual-gate FET, comprising the steps of:

forming a protrusion of a first semiconductor material on a substrate,
forming a first layer of a first material on sidewalls and a top surface of the protrusion,
forming a second layer of a second semiconductor material on the first layer,
removing a first portion of the first layer on the top surface of the protrusion and a first portion of the second layer on the first portion of the first layer to expose the top surface of the protrusion,
selectively removing a portion of the first material to a predetermined depth relative to the first and the second semiconductor material, to form a trench between the protrusion and the second layer, and to form a fin adjoining the trench, the fin formed from a portion of the second layer,
forming an insulation layer on the exposed surfaces of the trench and the fin, and
forming a layer of a conductive material on the insulation layer, thereby forming a gate electrode.

4 more elements

A method for fabricating a dual-gate FET, the method comprising:

forming a protrusion of a first semiconductor material on a substrate;
forming a first layer of a first material on sidewalls and a top surface of the protrusion;
forming a second layer of a second semiconductor material on the first layer;
removing a portion of the first layer and a portion of the second layer to expose the top surface of the protrusion;
selectively removing a portion of the first material to form a trench between the protrusion and a further portion of the second layer and to form a fin adjoining the trench, the fin formed from the further portion of the second layer and a remaining portion of the first material defining the bottom of the trench;
forming an insulation layer on the exposed surfaces of the trench and the fin;
and
forming a layer of a conductive material on the insulation layer, thereby forming a gate electrode.

5 more elements

Dependencies are inferred from the claim text.

Method of fabricating a dual gate FET

Life of this patent

Method of fabricating a dual gate FET

Life of this patent

Abstract

Claims17