Systems and methods for fabricating nanometric-scale semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks

A method comprising:

• providing a semiconductor wafer having an N-type metal-oxide (NMOS) region and a type metal-oxide (PMOS) region;
• depositing a first tensile material layer over the NMOS and PMOS regions;
• depositing a second tensile material layer over the first tensile material layer;
• forming a first photoresist over a first portion of the second tensile material layer above the NMOS region;
• removing a second portion of the second tensile material layer above the PMOS region;
• and
• removing a first portion of the first tensile material layer above the PMOS region.

A method comprising:

• providing a semiconductor device with an NMOS region and a PMOS region;
• selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region;
• and
• selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region.