Metal salicide formation having nitride liner to reduce silicide stringer and encroachment

A method of manufacturing a semiconductor device layout, the method comprising:

• forming an isolation trench in a semiconductor substrate to electrically isolate a semiconductor transistor formed on the substrate;
• forming a source/drain region in the substrate adjacent to and extending partially under a sidewall spacer of a gate electrode of the semiconductor transistor;
• depositing a non-metal protective layer over the device layout including over substantially all of the sidewall of the trench;
• filling the trench with a dielectric material to form an isolation structure;
• removing areas of the protective layer to form a first protective portion on the substrate at an intersection between the sidewall spacer and the source/drain region, wherein the first protective portion covers a portion of the source/drain region not extending under the sidewall spacer;
• removing areas of the protective layer to form a second protective portion on the semiconductor substrate distinct from the dielectric material filling the trench, the second protective portion extending from within the isolation structure and covering a portion of the source/drain region immediately adjacent to a perimeter of the isolation structure;
• depositing a metal layer over the layout;
• forming a metal silicide in the source/drain region by reacting the metal layer with silicon in the source/drain region, the first protective portion preventing the metal layer from reacting with the covered portion of the source/drain region not extending under the sidewall spacer such that no metal silicide forms at the intersection or in the portion of the source/drain region extending under the sidewall spacer, and the second protective portion protecting the immediately adjacent covered portion of the source/drain region from the deposited metal such that no metal silicide forms in the immediately adjacent covered portion;
• and
• removing non-reacted parts of the metal layer.

A method of manufacturing a semiconductor transistor layout, the method comprising:

• forming a source/drain region in a semiconductor substrate adjacent to and extending partially under a sidewall spacer of a gate electrode formed on the substrate;
• forming an isolation trench in the semiconductor substrate at an end of the source/drain region opposite the gate electrode to electrically isolate the transistor;
• forming a non-metal protective layer over the transistor layout including over substantially all of the sidewall of the trench;
• filling the trench with a dielectric material to form an isolation structure;
• removing areas of the protective layer to form a first protective portion extending from within the isolation structure to an upper surface of the source/drain region covering an upper portion of the source/drain region immediately adjacent to a perimeter of the isolation structure;
• depositing a metal layer over the layout;
• forming a metal silicide in the source/drain region by reacting the metal layer with silicon in the source/drain region, the first protective portion protecting the immediately adjacent covered portion of the source/drain region from the deposited metal such that no metal silicide forms in the immediately adjacent covered portion;
• and
• removing non-reacted parts of the metal layer.