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US 7,732,275 B2Granted
Methods of forming NAND flash memory with fixed charge
AssigneeSanDisk Corporation
InventorsTakashi Orimoto, George Matamis, Henry Chien, James Kai
Life of this patent
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Abstract
A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
Claims18
A method of forming a NAND flash memory array comprising:
- forming a first fixed charge layer that extends over a surface of a substrate;
- forming a plurality of floating gates overlying the first fixed charge layer;
- forming a plurality of conductive source/drain regions in areas of the substrate between floating gates, the source/drain regions connecting memory cells in series as a NAND string, the forming a first fixed charge layer includes adding charge to control the threshold voltage of the memory cells removing portions of the first fixed charge layer between the floating gates;
- and forming a second fixed charge layer having a negative charge between the plurality of floating gates after removing portions of the first fixed charge.
1 more element
A method of forming a NAND flash memory comprising:
- forming a dielectric layer over a surface of a substrate;
- performing a plasma nitridation process on the dielectric layer;
- forming a plurality of floating gates over the nitrided dielectric layer;
- removing portions of the nitrided dielectric layer that are not covered by the plurality of floating gates forming a fixed charge layer having a negative charge between the plurality of floating gates after removing the portions of the nitrided dielectric layer;
- and
- forming a plurality of control gates that are individually interposed between neighboring floating gates of the plurality of floating gates the control gates formed after forming the fixed charge layer.
3 more elements
A method of forming a NAND flash memory die comprising:
- forming a dielectric layer over a surface of a substrate;
- performing a plasma nitridation process on the dielectric layer;
- forming a plurality of floating gates over the nitrided dielectric layer, an individual one of the plurality of floating gates formed using a portion of a hard mask layer, the portion having a dimension that is less than the minimum feature size of a lithographic process used to pattern the hard mask layer, wherein the plasma nitridation process creates a first fixed charge layer that induces inversion layers in the substrate below the floating gates;
- removing portions of the first fixed charge layer between the floating gates;
- forming a second fixed charge layer having a negative charge between the plurality of floating gates after removing portions of the first fixed charge;
- and
- forming a plurality of control gates that are individually interposed between neighboring floating gates of the plurality of floating gates, the control gates formed after forming the second fixed charge layer.
4 more elements
Dependencies are inferred from the claim text.