Method for OPC model generation
AssigneeInfineon Technologies AG
InventorO Seo Park
Life of this patent
Estimating the term…
Abstract
A method for generating or refining an OPC model for use in wafer fabrication. A predetermined feature layout is used to prepare a mask for use in, for example, a photolithographic process. The mask is used to create structures corresponding to mask features on a semiconductor wafer using the mask. Measurements of the actual mask features and wafer features may then be assessed and correlated, and the results used to generate an OPC model or refine an existing one. In addition, the OPC may be used to simulate a fabrication operation by applying the OPC tool to a predetermined layout to produce a mask image and a wafer image, and then comparing the predetermined layout to the simulated wafer image to determine at least one fitness value.
Claims17
A method of refining an optical proximity correction (OPC) simulation tool for use in semiconductor fabrication, said method comprising the steps of:
- designing a mask having at least one feature from a predetermined layout;
- preparing a mask according to the mask design;
- simulating a fabrication operation to generate a simulated mask image according to the mask design;
- comparing the predetermined layout to the simulated mask image to determine at least one simulated mask error (ERRs);
- creating at least one structure corresponding to the at least one mask feature on a semiconductor wafer using the mask;
- measuring the at least one mask feature;
- measuring the at least one structure to determine its fidelity to the layout;
- comparing the measurements of the at least one mask feature and the at least one structure to determine at least one actual mask error (ERRm);
- comparing the simulated mask error (ERRs) to the actual mask error (ERRm) to determine at least one fitness value;
- determining, based at least in part on the at least one fitness value, whether to modify the mask design;
- and
- revising the OPC tool based on the results of the comparison of at least one of comparing the predetermined layout step or comparing the measurement step.
A method of forming a semiconductor device, said method comprising the steps of:
- designing a mask having at least one feature from a predetermined layout, the mask being designed using an optical proximity correction (OPC) simulation tool;
- preparing a mask according to the mask design;
- simulating a fabrication operation to generate a simulated mask image according to the mask design;
- comparing the predetermined layout to the simulated mask image to determine at least one simulated mask error (ERRs);
- creating at least one structure corresponding to the at least one mask feature on a semiconductor wafer using the mask;
- measuring the at least one mask feature;
- measuring the at least one structure to determine its fidelity to the layout;
- comparing the measurements of the at least one mask feature and the at least one structure to determine at least one actual mask error (ERRm);
- revising the OPC tool based on both the results of comparing the predetermined layout step and comparing measuring the at least one structure step;
- using the revised OPC tool to design a second mask;
- coating a resist material over a second semiconductor wafer;
- directing radiation through the second mask to irradiate portions of the resist;
- exposing portions of the second semiconductor wafer below the resist layer, the portions of the semiconductor wafer being exposed being related to the portions of the resist that were irradiated;
- and
- processing exposed portions of the semiconductor wafer.
Dependencies are inferred from the claim text.