Back to results
US 7,716,553 B2Granted
System and method for designing RS-based LDPC code decoder
AssigneeLeanics Corporation
InventorsSang-Min Kim, Keshab K. Parhi, Renfei Liu
Life of this patent
Estimating the term…
Abstract
A memory address generation method and circuit architecture for time-multiplexed RS-based LDPC code decoder is presented. The method is developed for non quasi-cyclic RS-based LDPC code decoder implementation. A circuit for the memory address generation method achieves low area. High throughput time-multiplexed RS-based LDPC code decoder design models and circuit architectures are presented. The decoder models are specifically developed for 10BASE-T (10-Gigabit Ethernet Transceiver Over Copper) system. These time-multiplexed architectures enable higher throughput with lower area.
Claims26
A Reed-Solomon code based low-density parity check code decoder, comprising:
- a check node unit (CNU) bank including a plurality of CNUs;
- a variable node unit (VNU) including a plurality of VNUs;
- a first memory address generator for CNU processing including a reference memory address block and an offset memory address block to generate a memory address from an exclusive-or of a reference memory address and an offset memory address;
- a second memory address generator for VNU processing including a counter;
- a memory unit addressed by a memory address generated by one of the first and second memory address generators;
- a data transfer channel between the memory unit and the VNU bank, and
- a data transfer channel between the memory unit and the CNU bank.
4 more elements
An integrated circuit to implement a Reed-Solomon (RS) code based low-density parity check code decoder, comprising:
- a check node unit (CNU) bank including a plurality of CNUs;
- a variable node unit (VNU) bank including a plurality of VNUs;
- a first memory address generator for CNU processing including a reference memory address block and an offset memory address block to generate a memory address from an exclusive-or of a reference memory address and an offset memory address;
- a second memory address generator for VNU processing including a counter;
- a memory unit addressed by a memory address generated by one of the first and second memory address generators;
- a data transfer channel between the memory unit and the VNU bank;
- and
- a data transfer channel between said memory unit and said CNU bank.
5 more elements
A decoder for decoding a low-density parity check (LDPC) code, comprising:
- (a) a CNU bank comprising a plurality of check node units (GNU's),
- (b) a VNU bank comprising a plurality of variable node units (VNU's),
- (c) a sign and sum accumulation unit (SSAU) bank comprising a plurality of SSAU units,
- (d) a first memory bank for storing extrinsic messages,
- (e) a second memory bank for storing intrinsic messages,
- (f) a first switch network transferring data from the said CNU bank to the said VNU bank,
- (g) a second switch network transferring data from the said VNU bank to the said first memory bank and to the said sign and sum accumulation unit bank,
- (h) check node units coupled to the first memory bank and to the SSAU unit bank, comprising:
- i. at least one lookup table (LUT),
- (i) variable node units coupled to the first switch network and the said second memory bank,
- (j) sign and sum accumulation unit (SSAU), for accumulating sign and sum of the check node messages, coupled to the second switch network comprising:
- i. one sign accumulation unit and one sum accumulation unit.
9 more elements
An integrated circuit having a substrate and a decoder for low-density parity check code disposed on said substrate, said decoder comprising:
- (a) a CNU bank comprising a plurality of check node units (CNU's),
- (b) a VNU bank comprising a plurality of variable node units (VNU's),
- (c) a sign and sum accumulation unit (SSAU) bank comprising a plurality of SSAU units,
- (d) a first memory unit for storing extrinsic messages,
- (e) a second memory unit for storing intrinsic messages,
- (f) a first switch network transferring data from the said CNU bank to the said VNU bank, a second switch network transferring data from the said VNU bank to the said first memory bank and to the said sign and sum accumulation unit bank,
- (g) check node units coupled to the first memory bank and to the SSAU unit bank, comprising:
- i. at least one lookup table (LUT),
- (h) variable node units coupled to the first switch network and the said second memory bank,
- (i) sign and sum accumulation unit (SSAU), for accumulating sign and sum of the check node messages, coupled to the second switch network comprising:
- i. one sign accumulation unit and one sum accumulation unit.
8 more elements
A decoder for decoding a low-density parity check (LDPC) code, comprising:
- (a) a CNU bank comprising a plurality of check node units (CNU's),
- (b) a VNU bank comprising a plurality of variable node units (VNU's),
- (c) a first memory bank for storing extrinsic messages, coupled to the said CNU bank,
- (d) a second memory bank, for storing intrinsic messages, whose output is coupled to the VNU bank,
- (e) a first switch network, transferring data from the said first memory bank to the said VNU bank, comprising a plurality of demultiplexers,
- (f) a second switch network, transferring data from the said VNU bank to the said first memory bank, comprising a plurality of demultiplexers,
- (g) check node units coupled to the said first memory bank,
- (h) variable node units coupled to the said first switch network and the said second memory bank.
5 more elements
An integrated circuit having a substrate and a decoder for a low-density parity check code disposed on said substrate, said decoder comprising:
- (a) a CNU bank comprising a plurality of check node units (CNU's),
- (b) a VNU bank comprising a plurality of variable node units (VNU's),
- (c) a first memory bank for storing extrinsic messages, coupled to the said CNU bank,
- (d) a second memory bank, for storing intrinsic messages, whose output is coupled to the VNU bank,
- (e) a first switch network, transferring data from the said first memory bank to the said VNU bank, comprising a plurality of demultiplexers,
- (f) a second switch network, transferring data from the said VNU bank to the said first memory bank, comprising a plurality of demultiplexers,
- (g) check node units coupled to the first memory bank,
- (h) variable node units coupled to the said first switch network and the said second memory bank.
5 more elements
A decoder for decoding a low-density parity check (LDPC) code, comprising:
- (a) a CNU bank comprising a plurality of check node units (CNU's),
- (b) a VNU bank comprising a plurality of variable node units (VNU's),
- (c) a first memory bank for storing extrinsic messages, coupled to the said VNU bank,
- (d) a second memory bank, for storing intrinsic messages, whose output is coupled to the VNU bank,
- (e) a first switch network, transferring data from the said first memory bank to the said GNU bank, comprising a plurality of demultiplexers,
- (f) a second switch network, transferring data from the said CNU bank to the said first memory bank, comprising a plurality of demultiplexers,
- (g) check node units coupled to the first switch network,
- (h) variable node units coupled to the said first memory bank and the said second memory bank.
5 more elements
An integrated circuit having a substrate and a decoder for a low-density parity check code disposed on said substrate, said decoder comprising:
- (a) a CNU bank comprising a plurality of check node units (CNU's),
- (b) a VNU bank comprising a plurality of variable node units (VNUs),
- (c) a first memory bank for storing extrinsic messages, coupled to the said VNU bank,
- (d) a second memory bank, for storing intrinsic messages, whose output is coupled to the VNU bank,
- (e) a first switch network, transferring data from the said first memory bank to the said CNU bank, comprising a plurality of demultiplexers,
- (f) a second switch network, transferring data from the said CNU bank to the said first memory bank, comprising a plurality of demultiplexers,
- (g) check node units coupled to the first switch network,
- (h) variable node units coupled to the said first memory bank and the said second memory bank.
5 more elements
Dependencies are inferred from the claim text.