AFSM circuit and method for low jitter PLL CMOS programmable divider

A method for dividing a clock signal, comprising:

• generating at least one phase signal which is a divided-down representation of the input clock signal and which includes information representative of a plurality phase signals, wherein each of the plurality of phase signals is a divided-down representation of the input clock signal, and wherein each of the plurality of phase signals is phase-shifted by a predetermined amount with respect to another of the plurality of phase signals;
• and
• generating a plurality of regenerated phase signals based at least in part on the at least one phase signal;
• generating a plurality of MSBs and a plurality of LSBs from dynamic divide ratio information;
• partially determining a programmable amount of delay between a pulse of the input clock signal and a subsequent corresponding pulse of an output clock signal by counting down from a value of the MSBs to a terminal count value, wherein a count value is based at least in part on at least one of the regenerated phase signals;
• generating a plurality control signal based part on the count value;
• and
• decoding the control signals to generate the output clock signal.

An apparatus comprising:

• a counter that receives a input clock signal and that generates a plurality of phase signals;
• programmable circuitry having:
• a phase regeneration circuit that is coupled to counter so as to receive at least one of the phase signals;
• a down counter that receives at least a portion of a divide ratio signal and that is coupled to the phase regeneration circuit;
• control logic that is coupled to the down counter;
• a decoder that is coupled to the control logic;
• phase shaping circuit that is coupled to the decoder;
• output circuit that is coupled to the phase shaping circuit, wherein the output clock signal outputs an output clock signal that is an divided-down representation of the input clock signal.