Method for producing an integrated circuit including a fuse element, a fuse-memory element or a resistor element
AssigneeInfineon Technologies AG
InventorsGeorg Seidemann, Reinhard Goellner
Life of this patent
Estimating the term…
Abstract
A method for producing an integrated circuit including a fuse element, a fuse-memory element or a resistor element is disclosed. In one embodiment, at least one metallization layer is applied onto a substrate. A hard mask is applied onto the at least one metallization layer. The at least one metallization layer is wet chemically etched by using the hard mask and the fuse element. The fuse-memory element or the resistor element is formed in a region in which the at least one metallization layer has been etched.
Claims17
A method for producing an integrated circuit including a component, comprising:
- applying a first metallization layer at least locally onto a substrate, the first metallization layer having a bottom surface on the substrate, an opposing top surface, and side face;
- applying a second metallization layer onto the first metallization layer, the second metallization layer having a bottom surface on the top surface of the flrst metallization layer, an opposing top surface, and side faces;
- applying a hard mask directly onto the top surface of the second metallization layer and directly onto at least the side faces of the first and second metallization layers;
- opening the hard mask to expose a portion of the top surface of the second metallization layer and wet chemically etching the second metallization layer by using the hard mask, wherein remaining portions of the hard mask cover the side faces of the first and second metallization layers during the wet chemically etching.
A method, comprising:
- applying a first metallization layer at least locally onto a substrate, the first metallization layer having a first major surface on the substrate, an opposing second major surface, and side faces;
- applying an etch stop layer onto the first metallization layer, the etch stop layer having a first major surface on the second major surface of the first metallization layer, an opposing second major surface, and side faces;
- applying a second metallization layer onto the etch stop layer, the second metallization layer having a first major surface on the second major surface of the etch stop layer, an opposing second major surface, and side faces;
- applying a hard mask onto directly onto the second major surface of the second metallization layer and directly onto the side faces of the first and second metallization layers;
- and
- removing the second metallization layer in a region of at least one opening of the hard mask along the second major of the second metallization layer by using a wet chemical etching method, the side faces of the first and second metallization layers being covered by the hard mask during the wet chemical etching.
Dependencies are inferred from the claim text.