Method of forming isolation layer of semiconductor device

Abstract

There is provided a method of forming an isolation layer which prevents a failure from occurring depending on a difference in the area of the isolation layer during a planarization process of the isolation layer having a shallow trench isolation (STI) structure. The present invention implements a uniform isolation layer by forming a chemical mechanical polishing (CMP) stop layer on an isolation layer having a relatively large region and performing a planarization process using the CMP stop layer. In accordance with an embodiment of the present invention, an isolation layer is completed by: forming a buffer insulating layer on a silicon substrate and patterning the buffer insulating layer; selectively etching the silicon substrate and forming trenches including a relatively big region and a relatively narrow region; depositing a first insulating layer and a second insulating layer sequentially on a whole surface of the silicon substrate; selectively removing the second insulating layer and forming a chemical mechanical polishing (CMP) stop layer only on the relatively large trench region; planarizing the first insulating layer using the CMP stop layer; and removing all of the CMP stop layer and the buffer insulating layer and completing an isolation layer.

Dependencies are inferred from the claim text.