Semiconductor process and PMOS varactor

A method in the fabrication of an integrated circuit including a PMOS varactor and a vertical bipolar npn transistor, said method comprising the steps of:

• providing a p-doped substrate;
• forming a buried n+-doped region for the npn transistor in said substrate;
• simultaneously forming in said substrate an essentially n-doped region for the PMOS varactor and an n-doped region above the buried n+-doped region for the npn transistor;
• simultaneously forming field isolation areas around, in a horizontal plane, said n-doped regions;
• forming a PMOS gate region on said essentially n-doped region for the PMOS varactor;
• forming a p-doped base in the n-doped region above the buried n+-doped region for the npn transistor and an n-doped emitter in the p-doped base;
• forming an n-doped collector contact to the buried n+-doped region for the npn transistor;
• said contact being separated from, in a horizontal plane, said n-doped regions;
• forming at least one n+-doped region in said essentially n-doped region for the PMOS varactor, said at least one n+-doped region being separated from, in a horizontal plane, said PMOS gate region;
• and
• forming a gate terminal connected to the PMOS gate region and a bulk terminal connected to said at least one n+-doped region.