ESD protection for semiconductor products
AssigneeFairchild Semiconductor Corporation
InventorsJun Cai, Alvin Sugerman, Steven Park
Life of this patent
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AssigneeFairchild Semiconductor Corporation
InventorsJun Cai, Alvin Sugerman, Steven Park
Estimating the term…
A process for forming a vertical DMOS device with an ESD protection transistor that is configured for carrying a breakdown current includes the steps of masking a substrate of a first polarity type and forming spaced apart surface isolation regions. An insulated gate is formed between the spaced apart surface isolation regions. Selected portions of the surface regions between the gate and the surface isolation regions are heterodoped to form p-n junctions having retrograde doping profiles beneath the substrate surface thereby lowering the breakdown voltage beneath the heterodoped portions in order to direct a substantial portion of the breakdown current below the surface of the substrate and into the body of the substrate between the heterodoped regions. Source and drain regions are formed in the substrate surface on opposite sides of the gate.
A process for forming a device with an MOS ESD protection transistor, said process comprising:
A method of forming as ESD protection device comprising the steps of:
Dependencies are inferred from the claim text.