Method of fabricating flash memory device
AssigneeHynix Semiconductor Inc.
InventorsEun Soo Kim, Whee Won Cho, Seung Hee Hong
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Abstract
The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved.
Claims11
A method of fabricating a flash memory device, the method comprising:
- providing a semiconductor substrate comprising a select transistor and memory cells having junctions, wherein a width between of the memory cells is smaller than a width between the select transistor and a memory cell that is adjacent to the select transistor;
- forming a hard mask pattern on a surface of the select transistor, the memory cells, and the semiconductor substrate to generate an overhang, wherein voids are formed between the memory cells due to the overhang;
- performing a first etch process to remove a portion of the hard mask pattern formed on a bottom between the select transistor and the memory cells, thus exposing the junctions;
- performing a second etch process to remove a portion of the junction formed between the select transistor and the memory cells, without removing the voids between the memory cells;
- and
- forming an insulating layer to gap-fill regions between the adjacent select transistor and memory cells.
A method of fabricating a flash memory device, the method comprising:
- providing a semiconductor substrate comprising select lines and word lines having junctions formed in the semiconductor substrate, wherein a width between the word lines is smaller than a width between a select line and a word line that is adjacent to the select line, and the width between the select line and the word line is smaller than a width between adjacent select lines;
- forming a hard mask pattern on a surface of the select lines, the word lines, and the semiconductor substrate including the junctions to generate an overhang, wherein voids are formed between the word lines due to the overhang;
- performing a first etch process to expose the junction between the select line and the word line which is adjacent to the select line;
- performing a second etch process to remove a portion of the junction formed between the adjacent select line and word line, without removing the voids between the word lines, and without removing the hard mask pattern formed on the junction between the adjacent select lines;
- and
- forming an insulating layer on the semiconductor substrate including the select lines, the word lines, and the junctions.
Dependencies are inferred from the claim text.