US 7,682,897 B2Granted

DRAM fabrication method using oxidation spacers on pillar dielectric sidewalls

AssigneeNanya Technology Corporation

InventorsChih-Huang Wu, Chien-Jung Yang

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Abstract

A process for fabricating a dynamic random access memory is provided. In this fabrication process, the steps of forming the silicon layer, and performing the ion implantation process and the removing process are repeated at least twice and the oxidation process is performed once to form an oxidation spacer that is larger than the landing area for a bit line contact in the prior art. Therefore, when defining a bit line contact opening, a larger process window is fabricated to prevent the occurrence of a short between the bit line contact and the gate of a transistor due to misalignment.

Claims13

Dependent claims

A process for fabricating a dynamic random access memory, comprising:

forming a plurality of trenches in a substrate, wherein a trench capacitor is formed in each trench, a pillar dielectric layer is formed on the trench capacitor, and the upper surface of the pillar dielectric layer protrudes from the surface of the substrate;
forming a silicon nitride layer and a first silicon layer sequentially on the substrate to conformably cover the pillar dielectric layer, wherein the thickness of the first silicon layer is smaller than that of a design rule for optimization of fabrication;
performing a first ion implantation process to implant ions into the first silicon layer disposed on top of the pillar dielectric layer and on the two sidewalls of the pillar dielectric layer, wherein ions are diffused into the first silicon layer disposed on the two sidewalls of the pillar dielectric layer to form a first doped region;
performing a first removing process to remove the first silicon layer disposed on top of the pillar dielectric layer and the first silicon layer on the two sidewalls of the pillar dielectric layer, but retain the first doped region;
forming a second silicon layer on the substrate to conformably cover the silicon nitride layer and the first doped region, wherein the thickness of the second silicon layer is smaller than that of a design rule for optimization of fabrication;
performing a second ion implantation process to implant ions into the second silicon layer disposed on top of the pillar dielectric layer and on the two sidewalls of the pillar dielectric layer, wherein ions are diffused into the second silicon layer disposed on the two sidewalls of the pillar dielectric layer to form a second doped region;
performing a second removing process to remove the second silicon layer disposed on top of the pillar dielectric layer and the second silicon layer on the two sidewalls of the pillar dielectric layer, but retain the second doped region;
and
performing an oxidation process to the first doped region and the second doped region to form an oxidation spacer on the sidewalls of the pillar dielectric layer.

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Dependencies are inferred from the claim text.

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Abstract

A process for fabricating a dynamic random access memory, comprising:

forming a plurality of trenches in a substrate, wherein a trench capacitor is formed in each trench, a pillar dielectric layer is formed on the trench capacitor, and the upper surface of the pillar dielectric layer protrudes from the surface of the substrate;
forming a silicon nitride layer and a first silicon layer sequentially on the substrate to conformably cover the pillar dielectric layer, wherein the thickness of the first silicon layer is smaller than that of a design rule for optimization of fabrication;
performing a first ion implantation process to implant ions into the first silicon layer disposed on top of the pillar dielectric layer and on the two sidewalls of the pillar dielectric layer, wherein ions are diffused into the first silicon layer disposed on the two sidewalls of the pillar dielectric layer to form a first doped region;
performing a first removing process to remove the first silicon layer disposed on top of the pillar dielectric layer and the first silicon layer on the two sidewalls of the pillar dielectric layer, but retain the first doped region;
forming a second silicon layer on the substrate to conformably cover the silicon nitride layer and the first doped region, wherein the thickness of the second silicon layer is smaller than that of a design rule for optimization of fabrication;
performing a second ion implantation process to implant ions into the second silicon layer disposed on top of the pillar dielectric layer and on the two sidewalls of the pillar dielectric layer, wherein ions are diffused into the second silicon layer disposed on the two sidewalls of the pillar dielectric layer to form a second doped region;
performing a second removing process to remove the second silicon layer disposed on top of the pillar dielectric layer and the second silicon layer on the two sidewalls of the pillar dielectric layer, but retain the second doped region;
and
performing an oxidation process to the first doped region and the second doped region to form an oxidation spacer on the sidewalls of the pillar dielectric layer.

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