US 7,682,778 B2 · Methods of forming contact plugs in semiconductor devices

Abstract

Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.

Claims11

Dependent claims

A method of forming contact plugs comprising:

forming a plurality of groups of elongated active regions aligned along a longitudinal axis, each group being parallel to a first axis in a semiconductor substrate;
forming a plurality of evenly spaced gate lines parallel to a second axis, wherein the first and second axes intersect at an acute angle α;
forming an interlayer insulating layer between the plurality of gate lines;
forming a plurality of evenly spaced contact opening lines parallel to a third axis exposing portions of the plurality of gate lines and portions of the interlayer insulating layer between the adjacent gate lines;
forming contact plugs in contact with the exposed portions of the active regions between the plurality of gate lines;
and
removing an upper portion of the interlayer insulating layer to form a planarized surface, the removing of the upper portion exposing upper surfaces of the plurality of gate lines.

4 more elements

A method of forming contact plugs comprising:

forming a plurality of groups of elongated active regions aligned along a longitudinal axis, each group being parallel to a first axis in a semiconductor substrate;
forming a plurality of evenly spaced gate lines parallel to a second axis, wherein the first and second axes intersect at an acute angle α;
forming an insulating spacer on each sidewall of the plurality of gate lines;
forming an interlayer insulating layer between the plurality of gate lines;
removing an upper portion of the interlayer insulating layer to form a planarized surface;
forming a plurality of evenly spaced contact opening lines parallel to a third axis exposing portions of the plurality of gate lines and portions of the interlayer insulating layer between the adjacent gate lines on the planarized surface;
etching the exposed portions of the plurality of gate lines at a first etch rate R1 and etching the exposed portions of the interlayer insulating layer at a second etch rate R2 to form contact openings and expose portions of the active regions, wherein the first and second etch rates satisfy the expression R1<R2;
forming contact plugs in contact with the exposed portions of the active regions between the plurality of gate lines;
and
removing an upper portion of the interlayer insulating layer to form a planarized surface, the removing of the upper portion exposing upper surfaces of the plurality of gate lines.

7 more elements

Dependencies are inferred from the claim text.

Methods of forming contact plugs in semiconductor devices

Life of this patent

Methods of forming contact plugs in semiconductor devices

Life of this patent

Abstract

Claims11