Pattern layout for forming integrated circuit
AssigneeKabushiki Kaisha Toshiba
InventorsHiromitsu Mashita, Tadahito Fujisawa, Minoru Inomoto, Koji Hashimoto, Yasunobu Kai
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AssigneeKabushiki Kaisha Toshiba
InventorsHiromitsu Mashita, Tadahito Fujisawa, Minoru Inomoto, Koji Hashimoto, Yasunobu Kai
Estimating the term…
A pattern layout for forming an integrated circuit includes a first device pattern, a second device pattern, and an auxiliary pattern. The first device pattern includes a line and a space alternately arrayed on a fixed pitch having regular intervals in a first direction. The second device pattern is disposed on the fixed pitch and separated from the first device pattern in the first direction. The second device pattern has a pattern width an odd-number times larger than the regular intervals of the fixed pitch, wherein the odd-number is set to be three or more. The auxiliary pattern is disposed on the fixed pitch and within the second device pattern and configured not to be resolved by light exposure.
A pattern layout for forming an integrated circuit, the pattern layout comprising:
A photo-mask used for a light exposure process to form an integrated circuit, the photo-mask comprising:
A data creation method for a photo-mask, the method comprising:
Dependencies are inferred from the claim text.