Multi-terminal harmonic oscillator integrated circuit with frequency calibration and frequency configuration

#The present invention, in general, relates to oscillation or clocking signal generation, and more particularly, relates to a discrete integrated circuit having a three or four terminal configuration which provides a clock signal and timing/frequency reference which may be calibrated or configured for frequency accuracy and selection.

#Accurate clock generators or timing references have generally relied upon crystal oscillators, such as quartz oscillators, which provide a mechanical, resonant vibration at a particular frequency. The difficulty with such crystal oscillators is that they cannot be fabricated as part of the same integrated circuit (“IC”) that is to be driven by their clock signal. Microprocessors, for example, require a separate clock IC. As a consequence, virtually every circuit requiring an accurate clock signal requires an off-chip clock generator.

#There are several consequences for such non-integrated solutions. For example, because such a processor must be connected through outside circuitry (such as on a printed circuit board (PCB)), power dissipation is comparatively increased. In applications which rely on a finite power supply, such as battery power in mobile communications, such additional power dissipation is detrimental.

#The objects, features and advantages of the present invention will be more readily appreciated upon reference to the following disclosure when considered in conjunction with the accompanying drawings and examples which form a portion of the specification, wherein like reference numerals are used to identify identical or similar components in the various views, in which:

#FIG. 1 (or “FIG. 1”) is a block diagram illustrating an exemplary system embodiment in accordance with the teachings of the present invention.

#FIG. 2 (or “FIG. 2”) is a block diagram illustrating a first exemplary apparatus embodiment in accordance with the teachings of the present invention.

#While the present invention is susceptible of embodiment in many different forms, there are shown in the drawings and will be described herein in detail specific examples and embodiments thereof, with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the invention to the specific examples and embodiments illustrated, and that numerous variations or modifications from the described embodiments may be possible and are considered equivalent. In this respect, before explaining at least one embodiment consistent with the present invention in detail, it is to be understood that the invention is not limited in its application to the details of construction and to the arrangements of components set forth above and below, illustrated in the drawings, or as described in the examples. Methods, systems and apparatuses consistent with the present invention are capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein, as well as the abstract included below, are for the purposes of description and should not be regarded as limiting.

#As indicated above, the various embodiments of the invention provide numerous advantages, including the ability to integrate a highly accurate (over PVT and age), low-jitter, free-running and self-referencing clock generator and/or a timing and frequency reference with other circuitry, such as illustrated in FIG. 1. FIG. 1 is a block diagram illustrating an exemplary system embodiment 150 in accordance with the teachings of the present invention. As illustrated in FIG. 1, the system 150 is a single integrated circuit, having a clock generator and/or timing/frequency reference 100 of the present invention integrated monolithically with other, or second, circuitry 180, together with interface (I/F) (or input/output (I/O) circuitry) 120. The interface 120 will generally provide power, such as from a power supply (not illustrated), ground, and other lines or busses to the clock generator 100, such as for calibration and frequency selection. As illustrated, one or more output clock signals are provided on bus 125, as a plurality of frequencies, such as a first frequency (f0), a second frequency (f1), and so on, through an (n+1)th frequency (fn). In addition, a power conservation mode (or low power mode (LP)) is provided (also on bus 125). The second circuitry 180 (or the I/F 120) may also provide input into the clock generator 100, such as through selection signals (S0, S1, through Sn), and one or more calibration signals (C0, C1, through Cn). Alternatively, the selection signals (S0, S1, through Sn) and one or more calibration signals (C0, C1, through Cn) may be provided directly to the clock generator 100 through the interface 120, such as on bus 135, along with power (on line 140) and ground (on line 145).

#The clock generator and/or timing/frequency reference 100, in addition to a low power mode, has additional modes discussed in greater detail below. For example, in a clock mode, the apparatus 100 will provide one or more clock signals, as output signals, to the second circuitry 180. The second circuitry 180 may be any type or kind of circuitry, such as a microprocessor, a digital signal processor (“DSP”), a radio-frequency circuit, for example, or any other circuit which could utilize the one or more output clock signals. Also for example, in a timing or frequency reference mode, the output signal from the apparatus 100 may be a reference signal, such as a reference signal for synchronization for a second oscillator. As a consequence, the terminology clock generator and/or timing/frequency reference will be utilized interchangeably herein, with the understanding that the clock generator will also generally provide a square-wave signal, which may or may not be provided with a timing/frequency reference, which may utilize a substantially sinusoidal signal instead. In addition, as discussed in greater detail below, the various embodiments of the invention also provided a pulsed mode, in which the output signal from clock generator and/or timing/frequency reference 100 is provided in bursts or intervals, for increased instruction processing efficiency and lower power consumption, for example.