Parametric testline with increased test pattern areas

#The present invention relates generally to the testing of integrated circuits, and more particularly to the structure of parametric testline on an integrated circuit wafer substrate for wafer acceptance testing (WAT), process control monitoring (PCM) and other R&D testing needs.

#In integrated circuit (IC) manufacturing, a semiconductor wafer typically contains a plurality of testlines in the scribe line area between adjacent wafer dies. Each testline includes a number of devices under test (DUTs), which are structures similar to those that are normally used to form the integrated circuit products in the wafer die area. DUTs are usually formed in the test pattern areas between adjacent probe pads on a testline at the same time as the functional circuitry using the same process steps. Probe pads are usually flat, square metal surfaces on a testline through which test stimuli can be applied to corresponding DUTs. Parametric test results on DUTs are usually utilized to monitor, improve and refine a semiconductor manufacturing process. Yield of test structures on a testline is often used to predict the yield of functional integrated circuitries in the die area.

#Shown in FIG. 1A is a plan view of a portion of a semiconductor wafer substrate layer 5 on which conventional parametric testlines are formed. A parametric testline 20 is formed in a scribe line area 10 between adjacent wafer dies 15. Each testline is made up by a serial number of aligned probe pads. Each probe pad 25 has a square shape and may be made from metal or other electrically conductive materials. Probe pads on a testline are electrically connected to a plurality of DUTs 30 formed between adjacent probe pads beneath the probe pad layer. Pluralities of test lines with different DUTs are formed in scribe line areas across the substrate. The DUTs 30 are test structures in the form of resistors, capacitors, inductors, diodes, transistors, or the like, designed to measure device parameters, such as MOSFET Vt, contact/via chain resistance, sheet capacitance, gate oxide breakdown voltage, and the like. By studying these parameters, it is possible to monitor, improve and refine a semiconductor production process.

#For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

#FIG. 1A is a plan view of a conventional parametric testline formed on a semiconductor wafer substrate;

#FIG. 1B shows a schematic cross-section view of a portion of a conventional parametric testline;

#The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

#The present invention will be described with respect to preferred embodiments in a specific context, namely innovative parametric testline structures for wafer acceptance testing (WAT). The preferred embodiments of the present invention include testline structures offering larger test pattern areas in order to accommodate more DUTs and DUTs with large dimensions. The invention may also be applied to benefit other activities, such as process control monitoring (PCM), yield analysis, statistical split, design-of-experiment (DOE), and design-for-manufacturability (DFM), and the like.

#Shown in FIG. 2A is a plan view illustrating a DUT arrangement in a conventional parametric testline as shown in FIGS. 1A-1B. In FIG. 2A, an exemplary DUT 30 in the form of a serpentine resistor is formed in a test pattern area between probe pad 1 and probe pad 2 of testline 20. The serpentine resistor 30 is made by conductive materials used in devices in a functional integrated circuitry, such as metal, metal alloy, or doped polysilicon, and is electrically connected to pad 1 and pad 2. By measuring the sheet resistance of DUT 30, one can readily determine whether a device comprising a similar structure made by the same material in an integrated circuitry, formed in the wafer die area, will exhibit desired resistance value. As mentioned earlier, however, when the dimension of a parametric testline 20 is downsized following the trend of feature size scaling down on a semiconductor wafer, there gets to a point where fitting a DUT into a shrunk test pattern area is no longer possible and a new testline structure offering a larger test pattern area on a shrunk testline must be developed. It is worth emphasizing that, when technology upgrading continues, the need of integrating large size devices in an integrated circuitry is more realistic than trivial because the types and variety of semiconductor devices in an advanced integrated electronic system increase dramatically. Therefore, testline structure capable of accommodating large size DUTs in a shrunk testline provides practical meanings.