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US 7,679,195 B2Granted
PAD structure and method of testing
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHsien-Wei Chen
Life of this patent
Estimating the term…
Abstract
An interconnect structure includes: a plurality of dielectric layers having aligned process control monitor (PCM) pads, and a conductive structure above a topmost one of the PCM pads. The conductive structure electrically connects the topmost PCM pad to a device under test above a level of the topmost PCM pad. The conductive structure is sized and shaped so as to leave a majority portion of the topmost PCM pad exposed for access by a test probe.
Claims11
A wafer, comprising:
- a substrate having a plurality of integrated circuits formed above the substrate, and at least one scribe line between two of the integrated circuits;
- a plurality of dielectric layers formed in the at least one scribe line having aligned process control monitor (PCM) pads formed therein;
- a passivation layer in the at least one scribe line between the two integrated circuits, on a topmost one of the plurality of dielectric layers and above a level of the PCM pads, and
- a conductive structure in the at least one scribe line between the two integrated circuits, above a topmost one of the PCM pads, the conductive structure having a first portion on the passivation layer and contacting a device under test, the first portion being continuous with a contact portion extending vertically from the first portion to contact the topmost PCM pad, the contact portion having a thickness that is small relative to a length of the topmost PCM pad, the conductive structure sized and shaped to contact and cover a minority portion of the topmost PCM pad with a majority portion of the topmost PCM pad exposed for access by a circuit probe.
1 more element
A wafer, comprising:
- a substrate having a plurality of integrated circuits formed above the substrate, and at least one scribe line between two of the integrated circuits;
- a plurality of dielectric layers formed in the at least one scribe line having aligned process control monitor (PCM) pads formed therein;
- a passivation layer in the at least one scribe line between the two integrated circuits, on a topmost one of the plurality of dielectric layers and above a level of the PCM pads, and
- a conductive structure in the at least one scribe line between the two integrated circuits, above a topmost one of the PCM pads, the conductive structure including an L-shaped structure having a planar first portion arranged horizontally on the passivation layer and contacting a device under test, the first portion being continuous with a planar contact portion extending vertically from the first portion to contact the topmost PCM pad, the contact portion having a thickness that is small relative to a length of the topmost PCM pad, the conductive structure contacting and covering a minority portion of the topmost PCM pad with a majority portion of the topmost PCM pad exposed for access by a circuit probe.
1 more element
Dependencies are inferred from the claim text.