Semiconductor device including cover layer

#The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2005-0134356 (filed on Dec. 29, 2005), which is hereby incorporated by reference in its entirety.

#As semiconductors achieve higher levels of integration and ever faster switching speeds, metal wiring layers formed within the semiconductor devices are getting finer and using multiple layers. However, as the widths of the metal wiring layers are reduced, signal delays may occur due to a resistance and parasitic capacitance (RC) of the metal wirings, thus impeding high speed switching and processing in semiconductor devices. An increase in leakage currents may also occur, increasing power consumption.

#To reduce such signal delays, copper wiring may be employed instead of aluminum wiring. However, with the trend towards narrower wiring, parasitic capacitance between wiring increases, so that signal delays may occur even using copper wiring. To reduce the problem of RC delays, a low-k interlayer insulating film may be used between the wirings. As semiconductor devices get finer, a lower dielectric constant may improve performance significantly.

#Example FIG. 1 is a cross sectional view showing a metal line of a semiconductor device in accordance with embodiments;

#Example FIGS. 2 to 4 provide cross sectional views describing a method for forming the metal line of the semiconductor device in accordance with embodiments;

#Example FIG. 5 is a cross sectional view showing a metal line of a semiconductor device in accordance with embodiments;

#Referring to example FIG. 1, there is provided a cross sectional view showing a metal line of a semiconductor device in accordance embodiments.

#As shown in example FIG. 1, an etch stop layer 104 and an interlayer insulating film 106 are formed over a substrate 100. The substrate 100 may include individual devices (not shown) or a lower conductor 102.

#The lower conductor 102 may be formed of copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), platinum (Pt), or the like. The etch stop layer 104 may be made of SiN, SiH4, or the like. The interlayer insulating film 106 may be formed by depositing an organic or inorganic insulating material such as a fluorine silicate glass (FSG), an undoped silicate glass (USG), SiH4, a tetra ethylortho silicate (TEOS), in either a single layer or multiple sub-layers. Alternatively, the interlayer insulating film 106 may be formed of a low-k material such as a black diamond (BD) having a dielectric constant not greater than a value of about 3.0. The interlayer insulating film 106 may be configured to have pores to further reduce its dielectric constant.