Electronic cooling device and fabrication method thereof
AssigneeDongbu HiTek Co., Ltd.
InventorChang Hun Han
Life of this patent
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Abstract
Provided are an electronic cooling device and a fabrication method thereof. The method may include forming an insulating layer on a semiconductor substrate, forming first and second silicide layers on the insulating layer, forming separate paired p-type and n-type semiconductors on each of the first and second silicide layers, forming a first interlayer dielectric (ILD) layer on the p-type and n-type semiconductors, exposing top surfaces of the n-type and p-type semiconductors, forming a third silicide layer on one semiconductor on each of the first and second silicide layers, forming a second ILD layer on the third silicide layer, and etching the second and first ILD layers to form contact holes exposing top surfaces of the first and second silicide layers.
Claims16
A method of fabricating a device, comprising:
- forming a pair of p-type semiconductor bodies and a pair of n-type semiconductor bodies on each of first and second silicide patterns such that the p-type semiconductor bodies of the pair of p-type semiconductor bodies are separated from each other and the n-type semiconductor bodies of the pair of n-type semiconductor bodies are separated from each other;
- forming a first dielectric layer on the p-type and n-type semiconductor bodies, and exposing top surfaces of the n-type and p-type semiconductor bodies;
- forming a third silicide layer on a first one of the n-type semiconductor bodies on the first silicide layer and on a first one of the p-type semiconductor bodies on the second silicide layer;
- forming a second dielectric layer on the third silicide layer and on an uppermost surface of a second one of the p-type semiconductor bodies and a second one of the n-type semiconductor bodies;
- and
- etching the second and first dielectric layers to form a contact hole exposing top surfaces of the first and second silicide layers.
An electronic cooling device, comprising:
- an insulating layer on a semiconductor substrate;
- first and second silicide layers on the insulating layer;
- a pair of p-type semiconductor bodies on the first and second silicide layers;
- a pair of n-type semiconductor bodies on the first and second silicide layers, where the p-type semiconductor bodies of the pair of p-type semiconductor bodies are separated from each other and the n-type semiconductor bodies of the pair of n-type semiconductor bodies are separated from each other;
- a first dielectric layer between the p-type and n-type semiconductor bodies;
- a third silicide layer on a first one of the n-type semiconductor bodies on the first silicide layer and a first one of the p-type semiconductor bodies on the second silicide layer so as to connect the first one of the n-type semiconductor bodies on the first silicide layer to the first one of the p-type semiconductor bodies on the second silicide layer;
- a second dielectric layer on the third silicide layer and on an uppermost surface of a second one of the p-type semiconductor bodies and a second one of the n-type semiconductor bodies;
- and
- contact holes penetrating the first and second dielectric layers to expose top surfaces of the first and second silicide layers.
Dependencies are inferred from the claim text.